The interconnect tiles are 19×64 bits. The space on the left is unused by the interconnect tile, and contains data for whatever primitive is associated with the interconnect tile.
Used with CLB tiles and the corner tiles.
Cells: 1
spartan3 INT_CLB switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][6] MAIN[6][7] MAIN[7][0] MAIN[7][7] MAIN[6][3] MAIN[7][4] MAIN[6][2] MAIN[6][5] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][1] MAIN[6][0] MAIN[7][1] MAIN[7][6] MAIN[6][4] MAIN[7][3] MAIN[7][2] MAIN[7][5] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][9] MAIN[6][8] MAIN[7][15] MAIN[7][8] MAIN[6][12] MAIN[7][11] MAIN[6][13] MAIN[6][10] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][14] MAIN[6][15] MAIN[7][14] MAIN[7][9] MAIN[6][11] MAIN[7][12] MAIN[7][13] MAIN[7][10] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][22] MAIN[6][23] MAIN[7][16] MAIN[7][23] MAIN[6][19] MAIN[7][20] MAIN[6][18] MAIN[6][21] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][17] MAIN[6][16] MAIN[7][17] MAIN[7][22] MAIN[6][20] MAIN[7][19] MAIN[7][18] MAIN[7][21] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][25] MAIN[6][24] MAIN[7][31] MAIN[7][24] MAIN[6][28] MAIN[7][27] MAIN[6][29] MAIN[6][26] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][30] MAIN[6][31] MAIN[7][30] MAIN[7][25] MAIN[6][27] MAIN[7][28] MAIN[7][29] MAIN[7][26] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][38] MAIN[6][39] MAIN[7][32] MAIN[7][39] MAIN[6][35] MAIN[7][36] MAIN[6][34] MAIN[6][37] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][33] MAIN[6][32] MAIN[7][33] MAIN[7][38] MAIN[6][36] MAIN[7][35] MAIN[7][34] MAIN[7][37] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][41] MAIN[6][40] MAIN[7][47] MAIN[7][40] MAIN[6][44] MAIN[7][43] MAIN[6][45] MAIN[6][42] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][46] MAIN[6][47] MAIN[7][46] MAIN[7][41] MAIN[6][43] MAIN[7][44] MAIN[7][45] MAIN[7][42] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][54] MAIN[6][55] MAIN[7][48] MAIN[7][55] MAIN[6][51] MAIN[7][52] MAIN[6][50] MAIN[6][53] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][49] MAIN[6][48] MAIN[7][49] MAIN[7][54] MAIN[6][52] MAIN[7][51] MAIN[7][50] MAIN[7][53] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][57] MAIN[6][56] MAIN[7][63] MAIN[7][56] MAIN[6][60] MAIN[7][59] MAIN[6][61] MAIN[6][58] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][62] MAIN[6][63] MAIN[7][62] MAIN[7][57] MAIN[6][59] MAIN[7][60] MAIN[7][61] MAIN[7][58] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_CLB switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_CLB switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_CLB switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_CLB switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_CLB switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_CLB switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_CLB switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_CLB switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_CLB switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_CLB switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_CLB switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_CLB switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_CLB switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_CLB switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_CLB switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_CLB switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_CLB switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_CLB switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_CLB switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_CLB switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_CLB switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_CLB switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_CLB switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_CLB switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_CLB switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_CLB switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_CLB switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_CLB switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_CLB switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_CLB switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_CLB switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_CLB switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[0]
Bits Destination
MAIN[5][24] MAIN[5][25] MAIN[4][24] MAIN[4][26] MAIN[4][21] MAIN[4][23] MAIN[5][23] MAIN[4][20] MAIN[4][16] MAIN[5][19] IMUX_CLK[0]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[3]
Bits Destination
MAIN[4][62] MAIN[4][63] MAIN[5][60] MAIN[4][60] MAIN[5][62] MAIN[5][59] IMUX_CE[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with CLB tiles and the corner tiles — FPGAcore variant.
Cells: 1
spartan3 INT_CLB_FC switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][6] MAIN[6][7] MAIN[7][0] MAIN[7][7] MAIN[6][3] MAIN[7][4] MAIN[6][2] MAIN[6][5] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][1] MAIN[6][0] MAIN[7][1] MAIN[7][6] MAIN[6][4] MAIN[7][3] MAIN[7][2] MAIN[7][5] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][9] MAIN[6][8] MAIN[7][15] MAIN[7][8] MAIN[6][12] MAIN[7][11] MAIN[6][13] MAIN[6][10] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][14] MAIN[6][15] MAIN[7][14] MAIN[7][9] MAIN[6][11] MAIN[7][12] MAIN[7][13] MAIN[7][10] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][22] MAIN[6][23] MAIN[7][16] MAIN[7][23] MAIN[6][19] MAIN[7][20] MAIN[6][18] MAIN[6][21] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][17] MAIN[6][16] MAIN[7][17] MAIN[7][22] MAIN[6][20] MAIN[7][19] MAIN[7][18] MAIN[7][21] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][25] MAIN[6][24] MAIN[7][31] MAIN[7][24] MAIN[6][28] MAIN[7][27] MAIN[6][29] MAIN[6][26] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][30] MAIN[6][31] MAIN[7][30] MAIN[7][25] MAIN[6][27] MAIN[7][28] MAIN[7][29] MAIN[7][26] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][38] MAIN[6][39] MAIN[7][32] MAIN[7][39] MAIN[6][35] MAIN[7][36] MAIN[6][34] MAIN[6][37] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][33] MAIN[6][32] MAIN[7][33] MAIN[7][38] MAIN[6][36] MAIN[7][35] MAIN[7][34] MAIN[7][37] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][41] MAIN[6][40] MAIN[7][47] MAIN[7][40] MAIN[6][44] MAIN[7][43] MAIN[6][45] MAIN[6][42] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][46] MAIN[6][47] MAIN[7][46] MAIN[7][41] MAIN[6][43] MAIN[7][44] MAIN[7][45] MAIN[7][42] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][54] MAIN[6][55] MAIN[7][48] MAIN[7][55] MAIN[6][51] MAIN[7][52] MAIN[6][50] MAIN[6][53] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][49] MAIN[6][48] MAIN[7][49] MAIN[7][54] MAIN[6][52] MAIN[7][51] MAIN[7][50] MAIN[7][53] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][57] MAIN[6][56] MAIN[7][63] MAIN[7][56] MAIN[6][60] MAIN[7][59] MAIN[6][61] MAIN[6][58] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][62] MAIN[6][63] MAIN[7][62] MAIN[7][57] MAIN[6][59] MAIN[7][60] MAIN[7][61] MAIN[7][58] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[0]
Bits Destination
MAIN[5][24] MAIN[5][25] MAIN[4][24] MAIN[4][26] MAIN[4][21] MAIN[4][23] MAIN[5][23] MAIN[4][20] MAIN[4][16] MAIN[5][19] IMUX_CLK[0]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[3]
Bits Destination
MAIN[4][62] MAIN[4][63] MAIN[5][60] MAIN[4][60] MAIN[5][62] MAIN[5][59] IMUX_CE[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with IOI tiles on Spartan 3.
Cells: 1
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][6] MAIN[6][7] MAIN[6][3] MAIN[7][0] MAIN[7][7] MAIN[7][4] MAIN[6][2] MAIN[6][5] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[5]
0 0 0 1 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 1 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 1 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 1 0 0 0 0 0 OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][1] MAIN[6][0] MAIN[6][4] MAIN[7][1] MAIN[7][6] MAIN[7][3] MAIN[7][2] MAIN[7][5] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[5]
0 0 0 1 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 1 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 1 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 1 0 0 0 0 0 OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[0]
Bits Destination
MAIN[4][23] MAIN[4][22] MAIN[5][23] MAIN[5][16] MAIN[4][18] MAIN[5][20] MAIN[4][19] MAIN[4][21] IMUX_IOCLK[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[1]
Bits Destination
MAIN[4][16] MAIN[4][17] MAIN[5][22] MAIN[5][17] MAIN[5][18] MAIN[5][19] MAIN[4][20] MAIN[5][21] IMUX_IOCLK[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[2]
Bits Destination
MAIN[4][24] MAIN[4][25] MAIN[5][24] MAIN[5][31] MAIN[4][29] MAIN[5][27] MAIN[4][28] MAIN[4][26] IMUX_IOCLK[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[3]
Bits Destination
MAIN[4][31] MAIN[4][30] MAIN[5][25] MAIN[5][30] MAIN[5][29] MAIN[5][28] MAIN[4][27] MAIN[5][26] IMUX_IOCLK[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[4]
Bits Destination
MAIN[4][39] MAIN[4][38] MAIN[5][39] MAIN[5][32] MAIN[4][34] MAIN[5][36] MAIN[4][35] MAIN[4][37] IMUX_IOCLK[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[5]
Bits Destination
MAIN[4][32] MAIN[4][33] MAIN[5][38] MAIN[5][33] MAIN[5][34] MAIN[5][35] MAIN[4][36] MAIN[5][37] IMUX_IOCLK[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[6]
Bits Destination
MAIN[4][40] MAIN[4][41] MAIN[5][40] MAIN[5][47] MAIN[4][45] MAIN[5][43] MAIN[4][44] MAIN[4][42] IMUX_IOCLK[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[7]
Bits Destination
MAIN[4][47] MAIN[4][46] MAIN[5][41] MAIN[5][46] MAIN[5][45] MAIN[5][44] MAIN[4][43] MAIN[5][42] IMUX_IOCLK[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
Used with IOI tiles on FPGAcore.
Cells: 1
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[3]
Bits Destination
MAIN[4][62] MAIN[4][63] MAIN[5][60] MAIN[4][60] MAIN[5][62] MAIN[5][59] IMUX_CE[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[0]
Bits Destination
MAIN[4][23] MAIN[4][22] MAIN[5][23] MAIN[5][16] MAIN[4][18] MAIN[5][20] MAIN[4][19] MAIN[4][21] IMUX_IOCLK[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[1]
Bits Destination
MAIN[4][16] MAIN[4][17] MAIN[5][22] MAIN[5][17] MAIN[5][18] MAIN[5][19] MAIN[4][20] MAIN[5][21] IMUX_IOCLK[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[2]
Bits Destination
MAIN[4][39] MAIN[4][38] MAIN[5][39] MAIN[5][32] MAIN[4][34] MAIN[5][36] MAIN[4][35] MAIN[4][37] IMUX_IOCLK[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[3]
Bits Destination
MAIN[4][32] MAIN[4][33] MAIN[5][38] MAIN[5][33] MAIN[5][34] MAIN[5][35] MAIN[4][36] MAIN[5][37] IMUX_IOCLK[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[4]
Bits Destination
MAIN[4][24] MAIN[4][25] MAIN[5][24] MAIN[5][31] MAIN[4][29] MAIN[5][27] MAIN[4][28] MAIN[4][26] IMUX_IOCLK[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[5]
Bits Destination
MAIN[4][31] MAIN[4][30] MAIN[5][25] MAIN[5][30] MAIN[5][29] MAIN[5][28] MAIN[4][27] MAIN[5][26] IMUX_IOCLK[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[6]
Bits Destination
MAIN[4][40] MAIN[4][41] MAIN[5][40] MAIN[5][47] MAIN[4][45] MAIN[5][43] MAIN[4][44] MAIN[4][42] IMUX_IOCLK[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[7]
Bits Destination
MAIN[4][47] MAIN[4][46] MAIN[5][41] MAIN[5][46] MAIN[5][45] MAIN[5][44] MAIN[4][43] MAIN[5][42] IMUX_IOCLK[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with IOI tiles on Spartan 3E.
Cells: 1
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][6] MAIN[6][7] MAIN[7][0] MAIN[7][7] MAIN[6][3] MAIN[7][4] MAIN[6][2] MAIN[6][5] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][1] MAIN[6][0] MAIN[7][1] MAIN[7][6] MAIN[6][4] MAIN[7][3] MAIN[7][2] MAIN[7][5] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][9] MAIN[6][8] MAIN[7][15] MAIN[7][8] MAIN[6][12] MAIN[7][11] MAIN[6][13] MAIN[6][10] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][14] MAIN[6][15] MAIN[7][14] MAIN[7][9] MAIN[6][11] MAIN[7][12] MAIN[7][13] MAIN[7][10] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][22] MAIN[6][23] MAIN[7][16] MAIN[7][23] MAIN[6][19] MAIN[7][20] MAIN[6][18] MAIN[6][21] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][17] MAIN[6][16] MAIN[7][17] MAIN[7][22] MAIN[6][20] MAIN[7][19] MAIN[7][18] MAIN[7][21] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][25] MAIN[6][24] MAIN[7][31] MAIN[7][24] MAIN[6][28] MAIN[7][27] MAIN[6][29] MAIN[6][26] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][30] MAIN[6][31] MAIN[7][30] MAIN[7][25] MAIN[6][27] MAIN[7][28] MAIN[7][29] MAIN[7][26] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][38] MAIN[6][39] MAIN[7][32] MAIN[7][39] MAIN[6][35] MAIN[7][36] MAIN[6][34] MAIN[6][37] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][33] MAIN[6][32] MAIN[7][33] MAIN[7][38] MAIN[6][36] MAIN[7][35] MAIN[7][34] MAIN[7][37] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][41] MAIN[6][40] MAIN[7][47] MAIN[7][40] MAIN[6][44] MAIN[7][43] MAIN[6][45] MAIN[6][42] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][46] MAIN[6][47] MAIN[7][46] MAIN[7][41] MAIN[6][43] MAIN[7][44] MAIN[7][45] MAIN[7][42] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][54] MAIN[6][55] MAIN[7][48] MAIN[7][55] MAIN[6][51] MAIN[7][52] MAIN[6][50] MAIN[6][53] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][49] MAIN[6][48] MAIN[7][49] MAIN[7][54] MAIN[6][52] MAIN[7][51] MAIN[7][50] MAIN[7][53] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][57] MAIN[6][56] MAIN[7][63] MAIN[7][56] MAIN[6][60] MAIN[7][59] MAIN[6][61] MAIN[6][58] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][62] MAIN[6][63] MAIN[7][62] MAIN[7][57] MAIN[6][59] MAIN[7][60] MAIN[7][61] MAIN[7][58] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 1 0 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[0]
Bits Destination
MAIN[4][23] MAIN[4][22] MAIN[5][23] MAIN[5][16] MAIN[4][18] MAIN[5][20] MAIN[4][19] MAIN[4][21] IMUX_IOCLK[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[1]
Bits Destination
MAIN[4][16] MAIN[4][17] MAIN[5][22] MAIN[5][17] MAIN[5][18] MAIN[5][19] MAIN[4][20] MAIN[5][21] IMUX_IOCLK[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[2]
Bits Destination
MAIN[4][24] MAIN[4][25] MAIN[5][24] MAIN[5][31] MAIN[4][29] MAIN[5][27] MAIN[4][28] MAIN[4][26] IMUX_IOCLK[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[3]
Bits Destination
MAIN[4][31] MAIN[4][30] MAIN[5][25] MAIN[5][30] MAIN[5][29] MAIN[5][28] MAIN[4][27] MAIN[5][26] IMUX_IOCLK[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[4]
Bits Destination
MAIN[4][39] MAIN[4][38] MAIN[5][39] MAIN[5][32] MAIN[4][34] MAIN[5][36] MAIN[4][35] MAIN[4][37] IMUX_IOCLK[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[5]
Bits Destination
MAIN[4][32] MAIN[4][33] MAIN[5][38] MAIN[5][33] MAIN[5][34] MAIN[5][35] MAIN[4][36] MAIN[5][37] IMUX_IOCLK[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[6]
Bits Destination
MAIN[4][40] MAIN[4][41] MAIN[5][40] MAIN[5][47] MAIN[4][45] MAIN[5][43] MAIN[4][44] MAIN[4][42] IMUX_IOCLK[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[7]
Bits Destination
MAIN[4][47] MAIN[4][46] MAIN[5][41] MAIN[5][46] MAIN[5][45] MAIN[5][44] MAIN[4][43] MAIN[5][42] IMUX_IOCLK[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with IOI tiles on Spartan 3A / 3A DSP that are on the left or right edge of the device.
Cells: 1
spartan3 INT_IOI_S3A_WE switchbox INT programmable inverters
Destination Source Bit
IMUX_SR_OPTINV[0] IMUX_SR[0] !MAIN[5][6]
IMUX_SR_OPTINV[1] IMUX_SR[1] !MAIN[5][7]
IMUX_CE_OPTINV[0] IMUX_CE[0] !MAIN[5][56]
IMUX_CE_OPTINV[1] IMUX_CE[1] !MAIN[5][57]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][6] MAIN[6][7] MAIN[7][4] MAIN[7][0] MAIN[7][7] MAIN[6][3] MAIN[6][2] MAIN[6][5] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[3]
0 0 0 0 1 0 0 0 OUT_FAN[5]
0 0 0 1 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 1 0 0 0 OUT_SEC[9]
1 0 0 1 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[15]
1 1 0 1 0 0 0 0 OUT_FAN[7]
1 1 1 0 0 0 0 0 OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][1] MAIN[6][0] MAIN[7][3] MAIN[7][1] MAIN[7][6] MAIN[6][4] MAIN[7][2] MAIN[7][5] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[3]
0 0 0 0 1 0 0 0 OUT_FAN[5]
0 0 0 1 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 1 0 0 0 OUT_SEC[9]
1 0 0 1 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[15]
1 1 0 1 0 0 0 0 OUT_FAN[7]
1 1 1 0 0 0 0 0 OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][9] MAIN[6][8] MAIN[7][11] MAIN[7][15] MAIN[7][8] MAIN[6][12] MAIN[6][13] MAIN[6][10] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[3]
0 0 0 0 1 0 0 0 OUT_FAN[5]
0 0 0 1 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 1 0 0 0 OUT_SEC[9]
1 0 0 1 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[15]
1 1 0 1 0 0 0 0 OUT_FAN[7]
1 1 1 0 0 0 0 0 OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[0]
Bits Destination
MAIN[4][23] MAIN[4][22] MAIN[5][23] MAIN[5][16] MAIN[4][18] MAIN[5][20] MAIN[4][19] MAIN[4][21] IMUX_IOCLK[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[1]
Bits Destination
MAIN[4][16] MAIN[4][17] MAIN[5][22] MAIN[5][17] MAIN[5][18] MAIN[5][19] MAIN[4][20] MAIN[5][21] IMUX_IOCLK[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[2]
Bits Destination
MAIN[4][24] MAIN[4][25] MAIN[5][24] MAIN[5][31] MAIN[4][29] MAIN[5][27] MAIN[4][28] MAIN[4][26] IMUX_IOCLK[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[3]
Bits Destination
MAIN[4][31] MAIN[4][30] MAIN[5][25] MAIN[5][30] MAIN[5][29] MAIN[5][28] MAIN[4][27] MAIN[5][26] IMUX_IOCLK[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[4]
Bits Destination
MAIN[4][39] MAIN[4][38] MAIN[5][39] MAIN[5][32] MAIN[4][34] MAIN[5][36] MAIN[4][35] MAIN[4][37] IMUX_IOCLK[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[5]
Bits Destination
MAIN[4][32] MAIN[4][33] MAIN[5][38] MAIN[5][33] MAIN[5][34] MAIN[5][35] MAIN[4][36] MAIN[5][37] IMUX_IOCLK[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[6]
Bits Destination
MAIN[4][40] MAIN[4][41] MAIN[5][40] MAIN[5][47] MAIN[4][45] MAIN[5][43] MAIN[4][44] MAIN[4][42] IMUX_IOCLK[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[7]
Bits Destination
MAIN[4][47] MAIN[4][46] MAIN[5][41] MAIN[5][46] MAIN[5][45] MAIN[5][44] MAIN[4][43] MAIN[5][42] IMUX_IOCLK[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with IOI tiles on Spartan 3A / 3A DSP that are on the top or bottom edge of the device.
Cells: 1
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][6] MAIN[6][7] MAIN[6][3] MAIN[7][0] MAIN[7][7] MAIN[7][4] MAIN[6][2] MAIN[6][5] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[5]
0 0 0 1 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 1 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 1 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 1 0 0 0 0 0 OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][1] MAIN[6][0] MAIN[6][4] MAIN[7][1] MAIN[7][6] MAIN[7][3] MAIN[7][2] MAIN[7][5] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[5]
0 0 0 1 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 1 0 0 0 OUT_SEC[9]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 1 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 1 0 0 0 0 0 OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[0]
Bits Destination
MAIN[4][23] MAIN[4][22] MAIN[5][23] MAIN[5][16] MAIN[4][18] MAIN[5][20] MAIN[4][19] MAIN[4][21] IMUX_IOCLK[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[1]
Bits Destination
MAIN[4][16] MAIN[4][17] MAIN[5][22] MAIN[5][17] MAIN[5][18] MAIN[5][19] MAIN[4][20] MAIN[5][21] IMUX_IOCLK[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[2]
Bits Destination
MAIN[4][24] MAIN[4][25] MAIN[5][24] MAIN[5][31] MAIN[4][29] MAIN[5][27] MAIN[4][28] MAIN[4][26] IMUX_IOCLK[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[3]
Bits Destination
MAIN[4][31] MAIN[4][30] MAIN[5][25] MAIN[5][30] MAIN[5][29] MAIN[5][28] MAIN[4][27] MAIN[5][26] IMUX_IOCLK[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[4]
Bits Destination
MAIN[4][39] MAIN[4][38] MAIN[5][39] MAIN[5][32] MAIN[4][34] MAIN[5][36] MAIN[4][35] MAIN[4][37] IMUX_IOCLK[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[5]
Bits Destination
MAIN[4][32] MAIN[4][33] MAIN[5][38] MAIN[5][33] MAIN[5][34] MAIN[5][35] MAIN[4][36] MAIN[5][37] IMUX_IOCLK[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[6]
Bits Destination
MAIN[4][40] MAIN[4][41] MAIN[5][40] MAIN[5][47] MAIN[4][45] MAIN[5][43] MAIN[4][44] MAIN[4][42] IMUX_IOCLK[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[7]
Bits Destination
MAIN[4][47] MAIN[4][46] MAIN[5][41] MAIN[5][46] MAIN[5][45] MAIN[5][44] MAIN[4][43] MAIN[5][42] IMUX_IOCLK[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 HEX_N1[4]
0 0 0 0 0 0 1 0 HEX_S4[4]
0 0 0 0 0 1 0 0 HEX_N2[4]
0 0 0 0 1 0 0 0 HEX_S3[4]
0 0 0 1 0 0 0 0 HEX_N0[4]
0 0 1 0 0 0 0 0 HEX_S5[4]
0 1 0 0 0 0 0 1 GCLK[0]
0 1 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 1 0 0 HEX_N4[4]
0 1 0 0 1 0 0 0 HEX_S1[4]
0 1 0 1 0 0 0 0 HEX_S6[4]
0 1 1 0 0 0 0 0 DBL_W2[4]
1 0 0 0 0 0 0 1 DBL_E0[4]
1 0 0 0 0 0 1 0 GCLK[6]
1 0 0 0 0 1 0 0 GCLK[7]
1 0 0 0 1 0 0 0 DBL_E1[4]
1 0 0 1 0 0 0 0 DBL_W1[4]
1 0 1 0 0 0 0 0 HEX_N5[4]
1 1 0 0 0 0 0 1 GCLK[1]
1 1 0 0 0 0 1 0 GCLK[2]
1 1 0 0 0 1 0 0 GCLK[3]
1 1 0 0 1 0 0 0 GCLK[4]
1 1 0 1 0 0 0 0 GCLK[5]
1 1 1 0 0 0 0 0 HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[0]
0 0 0 0 0 1 0 1 DBL_S1[4]
0 0 0 0 0 1 1 0 OMUX_WS1
0 0 0 0 1 1 0 1 OMUX_SE3
0 0 0 0 1 1 1 0 OMUX_W9
0 0 0 1 0 0 0 1 DBL_S2[5]
0 0 0 1 0 0 1 0 DBL_W1[5]
0 0 0 1 1 0 0 1 DBL_N1[4]
0 0 0 1 1 0 1 0 DBL_W2[4]
0 0 0 1 1 1 0 1 DBL_N1[5]
0 0 0 1 1 1 1 0 DBL_N2[5]
0 0 1 0 0 0 0 0 IMUX_FAN_BX[1]
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 1 0 0 DBL_S2[4]
0 0 1 1 0 0 0 0 OMUX_E8
0 0 1 1 1 0 0 0 DBL_E1[4]
0 0 1 1 1 1 0 0 DBL_S0[4]
0 1 0 0 0 0 0 0 DBL_N2[4]
0 1 0 0 0 1 0 0 OMUX_N11
0 1 0 0 1 1 0 0 DBL_W2[5]
0 1 0 1 0 0 0 0 DBL_W0[4]
0 1 0 1 1 0 0 0 DBL_E2[4]
0 1 0 1 1 1 0 0 OUT_FAN[1]
1 0 0 0 0 0 0 0 OUT_FAN[6]
1 0 0 0 1 1 0 0 DBL_W1[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 0 0 1 1 0 0 0 DBL_E0[5]
1 0 0 1 1 1 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with BRAM_S3 tiles on Spartan 3.
Cells: 1
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][7] MAIN[6][6] MAIN[7][7] MAIN[6][5] MAIN[7][4] MAIN[6][3] MAIN[6][2] MAIN[7][0] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][0] MAIN[6][1] MAIN[7][6] MAIN[7][5] MAIN[7][3] MAIN[6][4] MAIN[7][2] MAIN[7][1] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][8] MAIN[6][9] MAIN[7][8] MAIN[6][10] MAIN[7][11] MAIN[6][12] MAIN[6][13] MAIN[7][15] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][15] MAIN[6][14] MAIN[7][9] MAIN[7][10] MAIN[7][12] MAIN[6][11] MAIN[7][13] MAIN[7][14] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][23] MAIN[6][22] MAIN[7][23] MAIN[6][21] MAIN[7][20] MAIN[6][19] MAIN[6][18] MAIN[7][16] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][16] MAIN[6][17] MAIN[7][22] MAIN[7][21] MAIN[7][19] MAIN[6][20] MAIN[7][18] MAIN[7][17] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][24] MAIN[6][25] MAIN[7][24] MAIN[6][26] MAIN[7][27] MAIN[6][28] MAIN[6][29] MAIN[7][31] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][31] MAIN[6][30] MAIN[7][25] MAIN[7][26] MAIN[7][28] MAIN[6][27] MAIN[7][29] MAIN[7][30] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][39] MAIN[6][38] MAIN[7][39] MAIN[6][37] MAIN[7][36] MAIN[6][35] MAIN[6][34] MAIN[7][32] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][32] MAIN[6][33] MAIN[7][38] MAIN[7][37] MAIN[7][35] MAIN[6][36] MAIN[7][34] MAIN[7][33] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][40] MAIN[6][41] MAIN[7][40] MAIN[6][42] MAIN[7][43] MAIN[6][44] MAIN[6][45] MAIN[7][47] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][47] MAIN[6][46] MAIN[7][41] MAIN[7][42] MAIN[7][44] MAIN[6][43] MAIN[7][45] MAIN[7][46] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][55] MAIN[6][54] MAIN[7][55] MAIN[6][53] MAIN[7][52] MAIN[6][51] MAIN[6][50] MAIN[7][48] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][48] MAIN[6][49] MAIN[7][54] MAIN[7][53] MAIN[7][51] MAIN[6][52] MAIN[7][50] MAIN[7][49] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][56] MAIN[6][57] MAIN[7][56] MAIN[6][58] MAIN[7][59] MAIN[6][60] MAIN[6][61] MAIN[7][63] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][63] MAIN[6][62] MAIN[7][57] MAIN[7][58] MAIN[7][60] MAIN[6][59] MAIN[7][61] MAIN[7][62] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CE[3]
Bits Destination
MAIN[4][62] MAIN[4][63] MAIN[5][60] MAIN[4][60] MAIN[5][62] MAIN[5][59] IMUX_CE[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with BRAM_S3E tiles on Spartan 3E.
Cells: 1
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][7] MAIN[6][6] MAIN[7][7] MAIN[6][5] MAIN[7][4] MAIN[6][3] MAIN[6][2] MAIN[7][0] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][0] MAIN[6][1] MAIN[7][6] MAIN[7][5] MAIN[7][3] MAIN[6][4] MAIN[7][2] MAIN[7][1] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][8] MAIN[6][9] MAIN[7][8] MAIN[6][10] MAIN[7][11] MAIN[6][12] MAIN[6][13] MAIN[7][15] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][15] MAIN[6][14] MAIN[7][9] MAIN[7][10] MAIN[7][12] MAIN[6][11] MAIN[7][13] MAIN[7][14] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][23] MAIN[6][22] MAIN[7][23] MAIN[6][21] MAIN[7][20] MAIN[6][19] MAIN[6][18] MAIN[7][16] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][16] MAIN[6][17] MAIN[7][22] MAIN[7][21] MAIN[7][19] MAIN[6][20] MAIN[7][18] MAIN[7][17] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][24] MAIN[6][25] MAIN[7][24] MAIN[6][26] MAIN[7][27] MAIN[6][28] MAIN[6][29] MAIN[7][31] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][31] MAIN[6][30] MAIN[7][25] MAIN[7][26] MAIN[7][28] MAIN[6][27] MAIN[7][29] MAIN[7][30] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][39] MAIN[6][38] MAIN[7][39] MAIN[6][37] MAIN[7][36] MAIN[6][35] MAIN[6][34] MAIN[7][32] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][32] MAIN[6][33] MAIN[7][38] MAIN[7][37] MAIN[7][35] MAIN[6][36] MAIN[7][34] MAIN[7][33] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][40] MAIN[6][41] MAIN[7][40] MAIN[6][42] MAIN[7][43] MAIN[6][44] MAIN[6][45] MAIN[7][47] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][47] MAIN[6][46] MAIN[7][41] MAIN[7][42] MAIN[7][44] MAIN[6][43] MAIN[7][45] MAIN[7][46] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][55] MAIN[6][54] MAIN[7][55] MAIN[6][53] MAIN[7][52] MAIN[6][51] MAIN[6][50] MAIN[7][48] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][48] MAIN[6][49] MAIN[7][54] MAIN[7][53] MAIN[7][51] MAIN[6][52] MAIN[7][50] MAIN[7][49] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][56] MAIN[6][57] MAIN[7][56] MAIN[6][58] MAIN[7][59] MAIN[6][60] MAIN[6][61] MAIN[7][63] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][63] MAIN[6][62] MAIN[7][57] MAIN[7][58] MAIN[7][60] MAIN[6][59] MAIN[7][61] MAIN[7][62] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[0]
Bits Destination
MAIN[5][24] MAIN[5][25] MAIN[4][24] MAIN[4][26] MAIN[4][21] MAIN[4][23] MAIN[5][23] MAIN[4][20] MAIN[4][16] MAIN[5][19] IMUX_CLK[0]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[3]
Bits Destination
MAIN[4][62] MAIN[4][63] MAIN[5][60] MAIN[4][60] MAIN[5][62] MAIN[5][59] IMUX_CE[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with BRAM_S3A tiles on Spartan 3A. This interconnect tile is used in rows 0 and 3 of the BRAM.
Cells: 1
spartan3 INT_BRAM_S3A_03 switchbox INT programmable inverters
Destination Source Bit
IMUX_SR_OPTINV[0] IMUX_SR[0] !MAIN[5][6]
IMUX_SR_OPTINV[1] IMUX_SR[1] !MAIN[5][7]
IMUX_SR_OPTINV[2] IMUX_SR[2] !MAIN[5][0]
IMUX_SR_OPTINV[3] IMUX_SR[3] !MAIN[5][13]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][7] MAIN[6][6] MAIN[7][7] MAIN[6][5] MAIN[7][4] MAIN[6][3] MAIN[6][2] MAIN[7][0] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][0] MAIN[6][1] MAIN[7][6] MAIN[7][5] MAIN[7][3] MAIN[6][4] MAIN[7][2] MAIN[7][1] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][8] MAIN[6][9] MAIN[7][8] MAIN[6][10] MAIN[7][11] MAIN[6][12] MAIN[6][13] MAIN[7][15] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][15] MAIN[6][14] MAIN[7][9] MAIN[7][10] MAIN[7][12] MAIN[6][11] MAIN[7][13] MAIN[7][14] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][23] MAIN[6][22] MAIN[7][23] MAIN[6][21] MAIN[7][20] MAIN[6][19] MAIN[6][18] MAIN[7][16] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][16] MAIN[6][17] MAIN[7][22] MAIN[7][21] MAIN[7][19] MAIN[6][20] MAIN[7][18] MAIN[7][17] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][24] MAIN[6][25] MAIN[7][24] MAIN[6][26] MAIN[7][27] MAIN[6][28] MAIN[6][29] MAIN[7][31] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][31] MAIN[6][30] MAIN[7][25] MAIN[7][26] MAIN[7][28] MAIN[6][27] MAIN[7][29] MAIN[7][30] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][39] MAIN[6][38] MAIN[7][39] MAIN[6][37] MAIN[7][36] MAIN[6][35] MAIN[6][34] MAIN[7][32] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][32] MAIN[6][33] MAIN[7][38] MAIN[7][37] MAIN[7][35] MAIN[6][36] MAIN[7][34] MAIN[7][33] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][40] MAIN[6][41] MAIN[7][40] MAIN[6][42] MAIN[7][43] MAIN[6][44] MAIN[6][45] MAIN[7][47] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][47] MAIN[6][46] MAIN[7][41] MAIN[7][42] MAIN[7][44] MAIN[6][43] MAIN[7][45] MAIN[7][46] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][55] MAIN[6][54] MAIN[7][55] MAIN[6][53] MAIN[7][52] MAIN[6][51] MAIN[6][50] MAIN[7][48] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][48] MAIN[6][49] MAIN[7][54] MAIN[7][53] MAIN[7][51] MAIN[6][52] MAIN[7][50] MAIN[7][49] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][56] MAIN[6][57] MAIN[7][56] MAIN[6][58] MAIN[7][59] MAIN[6][60] MAIN[6][61] MAIN[7][63] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][63] MAIN[6][62] MAIN[7][57] MAIN[7][58] MAIN[7][60] MAIN[6][59] MAIN[7][61] MAIN[7][62] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LV[12]
Bits Destination
MAIN[18][9] MAIN[18][14] MAIN[18][16] MAIN[18][15] MAIN[18][17] LV[12]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with BRAM_S3A tiles on Spartan 3A. This interconnect tile is used in rows 1 and 2 of the BRAM.
Cells: 1
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][7] MAIN[6][6] MAIN[7][7] MAIN[6][5] MAIN[7][4] MAIN[6][3] MAIN[6][2] MAIN[7][0] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][0] MAIN[6][1] MAIN[7][6] MAIN[7][5] MAIN[7][3] MAIN[6][4] MAIN[7][2] MAIN[7][1] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][8] MAIN[6][9] MAIN[7][8] MAIN[6][10] MAIN[7][11] MAIN[6][12] MAIN[6][13] MAIN[7][15] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][15] MAIN[6][14] MAIN[7][9] MAIN[7][10] MAIN[7][12] MAIN[6][11] MAIN[7][13] MAIN[7][14] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][23] MAIN[6][22] MAIN[7][23] MAIN[6][21] MAIN[7][20] MAIN[6][19] MAIN[6][18] MAIN[7][16] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][16] MAIN[6][17] MAIN[7][22] MAIN[7][21] MAIN[7][19] MAIN[6][20] MAIN[7][18] MAIN[7][17] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][24] MAIN[6][25] MAIN[7][24] MAIN[6][26] MAIN[7][27] MAIN[6][28] MAIN[6][29] MAIN[7][31] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][31] MAIN[6][30] MAIN[7][25] MAIN[7][26] MAIN[7][28] MAIN[6][27] MAIN[7][29] MAIN[7][30] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][39] MAIN[6][38] MAIN[7][39] MAIN[6][37] MAIN[7][36] MAIN[6][35] MAIN[6][34] MAIN[7][32] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][32] MAIN[6][33] MAIN[7][38] MAIN[7][37] MAIN[7][35] MAIN[6][36] MAIN[7][34] MAIN[7][33] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][40] MAIN[6][41] MAIN[7][40] MAIN[6][42] MAIN[7][43] MAIN[6][44] MAIN[6][45] MAIN[7][47] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][47] MAIN[6][46] MAIN[7][41] MAIN[7][42] MAIN[7][44] MAIN[6][43] MAIN[7][45] MAIN[7][46] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][55] MAIN[6][54] MAIN[7][55] MAIN[6][53] MAIN[7][52] MAIN[6][51] MAIN[6][50] MAIN[7][48] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][48] MAIN[6][49] MAIN[7][54] MAIN[7][53] MAIN[7][51] MAIN[6][52] MAIN[7][50] MAIN[7][49] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][56] MAIN[6][57] MAIN[7][56] MAIN[6][58] MAIN[7][59] MAIN[6][60] MAIN[6][61] MAIN[7][63] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][63] MAIN[6][62] MAIN[7][57] MAIN[7][58] MAIN[7][60] MAIN[6][59] MAIN[7][61] MAIN[7][62] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LV[12]
Bits Destination
MAIN[18][9] MAIN[18][14] MAIN[18][16] MAIN[18][15] MAIN[18][17] LV[12]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[0]
Bits Destination
MAIN[5][24] MAIN[5][25] MAIN[4][24] MAIN[4][26] MAIN[4][21] MAIN[4][23] MAIN[5][23] MAIN[4][20] MAIN[4][16] MAIN[5][19] IMUX_CLK[0]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[3]
Bits Destination
MAIN[4][62] MAIN[4][63] MAIN[5][60] MAIN[4][60] MAIN[5][62] MAIN[5][59] IMUX_CE[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with BRAM_S3ADSP or DSP tiles on Spartan 3A DSP.
Cells: 1
spartan3 INT_BRAM_S3ADSP switchbox INT permanent buffers
Destination Source
IMUX_FAN_BX_BOUNCE[0] IMUX_FAN_BX[0]
IMUX_FAN_BX_BOUNCE[1] IMUX_FAN_BX[1]
IMUX_FAN_BX_BOUNCE[2] IMUX_FAN_BX[2]
IMUX_FAN_BX_BOUNCE[3] IMUX_FAN_BX[3]
IMUX_FAN_BY_BOUNCE[0] IMUX_FAN_BY[0]
IMUX_FAN_BY_BOUNCE[1] IMUX_FAN_BY[1]
IMUX_FAN_BY_BOUNCE[2] IMUX_FAN_BY[2]
IMUX_FAN_BY_BOUNCE[3] IMUX_FAN_BY[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][7] MAIN[6][6] MAIN[7][7] MAIN[6][5] MAIN[7][4] MAIN[6][3] MAIN[6][2] MAIN[7][0] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][0] MAIN[6][1] MAIN[7][6] MAIN[7][5] MAIN[7][3] MAIN[6][4] MAIN[7][2] MAIN[7][1] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][8] MAIN[6][9] MAIN[7][8] MAIN[6][10] MAIN[7][11] MAIN[6][12] MAIN[6][13] MAIN[7][15] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][15] MAIN[6][14] MAIN[7][9] MAIN[7][10] MAIN[7][12] MAIN[6][11] MAIN[7][13] MAIN[7][14] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][23] MAIN[6][22] MAIN[7][23] MAIN[6][21] MAIN[7][20] MAIN[6][19] MAIN[6][18] MAIN[7][16] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][16] MAIN[6][17] MAIN[7][22] MAIN[7][21] MAIN[7][19] MAIN[6][20] MAIN[7][18] MAIN[7][17] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][24] MAIN[6][25] MAIN[7][24] MAIN[6][26] MAIN[7][27] MAIN[6][28] MAIN[6][29] MAIN[7][31] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][31] MAIN[6][30] MAIN[7][25] MAIN[7][26] MAIN[7][28] MAIN[6][27] MAIN[7][29] MAIN[7][30] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF0[1]
0 1 0 0 1 0 0 0 OUT_HALF0[0]
0 1 0 1 0 0 0 0 OUT_HALF0[2]
0 1 1 0 0 0 0 0 OUT_HALF0[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][39] MAIN[6][38] MAIN[7][39] MAIN[6][37] MAIN[7][36] MAIN[6][35] MAIN[6][34] MAIN[7][32] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][32] MAIN[6][33] MAIN[7][38] MAIN[7][37] MAIN[7][35] MAIN[6][36] MAIN[7][34] MAIN[7][33] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][40] MAIN[6][41] MAIN[7][40] MAIN[6][42] MAIN[7][43] MAIN[6][44] MAIN[6][45] MAIN[7][47] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][47] MAIN[6][46] MAIN[7][41] MAIN[7][42] MAIN[7][44] MAIN[6][43] MAIN[7][45] MAIN[7][46] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][55] MAIN[6][54] MAIN[7][55] MAIN[6][53] MAIN[7][52] MAIN[6][51] MAIN[6][50] MAIN[7][48] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][48] MAIN[6][49] MAIN[7][54] MAIN[7][53] MAIN[7][51] MAIN[6][52] MAIN[7][50] MAIN[7][49] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][56] MAIN[6][57] MAIN[7][56] MAIN[6][58] MAIN[7][59] MAIN[6][60] MAIN[6][61] MAIN[7][63] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][63] MAIN[6][62] MAIN[7][57] MAIN[7][58] MAIN[7][60] MAIN[6][59] MAIN[7][61] MAIN[7][62] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[4]
0 0 1 0 0 0 0 0 OUT_FAN[5]
0 1 0 0 0 0 0 1 OUT_FAN[6]
0 1 0 0 0 0 1 0 OUT_FAN[7]
0 1 0 0 0 1 0 0 OUT_HALF1[1]
0 1 0 0 1 0 0 0 OUT_HALF1[0]
0 1 0 1 0 0 0 0 OUT_HALF1[2]
0 1 1 0 0 0 0 0 OUT_HALF1[3]
1 0 0 0 0 0 0 1 OUT_SEC[4]
1 0 0 0 0 0 1 0 OUT_SEC[5]
1 0 0 0 0 1 0 0 OUT_SEC[7]
1 0 0 1 0 0 0 0 OUT_SEC[8]
1 0 1 0 0 0 0 0 OUT_SEC[9]
1 1 0 0 0 0 0 1 OUT_SEC[10]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[13]
1 1 0 0 1 0 0 0 OUT_SEC[12]
1 1 0 1 0 0 0 0 OUT_SEC[14]
1 1 1 0 0 0 0 0 OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LV[12]
Bits Destination
MAIN[18][9] MAIN[18][14] MAIN[18][16] MAIN[18][15] MAIN[18][17] LV[12]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[0]
Bits Destination
MAIN[5][24] MAIN[5][25] MAIN[4][24] MAIN[4][26] MAIN[4][21] MAIN[4][23] MAIN[5][23] MAIN[4][20] MAIN[4][16] MAIN[5][19] IMUX_CLK[0]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[0]
Bits Destination
MAIN[4][6] MAIN[4][5] MAIN[4][4] MAIN[5][5] MAIN[4][2] MAIN[5][2] IMUX_SR[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[1]
Bits Destination
MAIN[4][7] MAIN[4][8] MAIN[4][9] MAIN[5][9] MAIN[5][12] MAIN[4][11] IMUX_SR[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[2]
Bits Destination
MAIN[4][0] MAIN[4][1] MAIN[5][4] MAIN[4][3] MAIN[5][3] MAIN[5][1] IMUX_SR[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[0]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[0]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[0]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[3]
Bits Destination
MAIN[4][13] MAIN[4][12] MAIN[5][8] MAIN[4][10] MAIN[5][10] MAIN[5][11] IMUX_SR[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_E1[1]
0 0 0 0 1 0 HEX_S4[0]
0 0 0 1 0 0 HEX_S5[0]
0 0 1 0 0 0 HEX_S6[0]
0 1 0 0 0 1 DBL_W1[1]
0 1 0 0 1 0 HEX_N0[0]
0 1 0 1 0 0 HEX_N1[0]
0 1 1 0 0 0 HEX_N2[0]
1 0 0 0 0 1 DBL_E0[1]
1 0 0 0 1 0 HEX_S1[0]
1 0 0 1 0 0 HEX_S2[0]
1 0 1 0 0 0 HEX_S3[0]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 HEX_N3[0]
1 1 0 1 0 0 HEX_N4[0]
1 1 1 0 0 0 HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[0]
Bits Destination
MAIN[4][55] MAIN[4][56] MAIN[5][51] MAIN[5][54] MAIN[4][54] MAIN[4][52] IMUX_CE[0]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[1]
Bits Destination
MAIN[4][58] MAIN[4][57] MAIN[4][61] MAIN[5][58] MAIN[5][61] MAIN[4][59] IMUX_CE[1]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[2]
Bits Destination
MAIN[4][51] MAIN[4][50] MAIN[5][53] MAIN[4][53] MAIN[5][55] MAIN[5][52] IMUX_CE[2]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W2[6]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W1[6]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E1[6]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E0[6]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[3]
Bits Destination
MAIN[4][62] MAIN[4][63] MAIN[5][60] MAIN[4][60] MAIN[5][62] MAIN[5][59] IMUX_CE[3]
Source
0 0 0 0 0 0 PULLUP
0 0 0 0 0 1 DBL_W1[7]
0 0 0 0 1 0 HEX_N5[7]
0 0 0 1 0 0 HEX_N4[7]
0 0 1 0 0 0 HEX_N3[7]
0 1 0 0 0 1 DBL_W2[7]
0 1 0 0 1 0 HEX_N2[7]
0 1 0 1 0 0 HEX_N1[7]
0 1 1 0 0 0 HEX_N0[7]
1 0 0 0 0 1 DBL_E0[7]
1 0 0 0 1 0 HEX_S4[7]
1 0 0 1 0 0 HEX_S5[7]
1 0 1 0 0 0 HEX_S6[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 HEX_S1[7]
1 1 0 1 0 0 HEX_S2[7]
1 1 1 0 0 0 HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[0]
Bits Destination
MAIN[9][42] MAIN[9][40] MAIN[9][41] MAIN[10][43] MAIN[8][45] MAIN[9][39] MAIN[8][39] MAIN[10][39] IMUX_DATA[0]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[1]
Bits Destination
MAIN[12][10] MAIN[12][8] MAIN[12][9] MAIN[11][7] MAIN[11][12] MAIN[10][11] MAIN[10][9] MAIN[12][11] IMUX_DATA[1]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[4]
Bits Destination
MAIN[8][1] MAIN[8][2] MAIN[8][3] MAIN[8][4] MAIN[10][2] MAIN[9][0] MAIN[10][6] MAIN[9][4] IMUX_DATA[4]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[5]
Bits Destination
MAIN[11][48] MAIN[11][47] MAIN[11][46] MAIN[11][45] MAIN[12][51] MAIN[11][50] MAIN[12][50] MAIN[10][44] IMUX_DATA[5]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[6]
Bits Destination
MAIN[8][14] MAIN[8][16] MAIN[8][15] MAIN[8][17] MAIN[10][15] MAIN[9][14] MAIN[9][19] MAIN[10][16] IMUX_DATA[6]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[7]
Bits Destination
MAIN[11][60] MAIN[11][61] MAIN[11][62] MAIN[11][58] MAIN[12][63] MAIN[10][63] MAIN[12][58] MAIN[10][58] IMUX_DATA[7]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[8]
Bits Destination
MAIN[11][42] MAIN[11][41] MAIN[11][40] MAIN[11][39] MAIN[12][45] MAIN[10][42] MAIN[12][39] MAIN[10][38] IMUX_DATA[8]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[9]
Bits Destination
MAIN[8][10] MAIN[8][8] MAIN[8][9] MAIN[8][11] MAIN[10][8] MAIN[9][7] MAIN[9][12] MAIN[10][10] IMUX_DATA[9]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[10]
Bits Destination
MAIN[11][54] MAIN[11][55] MAIN[11][53] MAIN[11][52] MAIN[12][57] MAIN[11][57] MAIN[12][56] MAIN[10][50] IMUX_DATA[10]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[11]
Bits Destination
MAIN[8][20] MAIN[8][22] MAIN[8][21] MAIN[8][23] MAIN[8][19] MAIN[9][20] MAIN[9][25] MAIN[10][22] IMUX_DATA[11]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[12]
Bits Destination
MAIN[12][1] MAIN[12][2] MAIN[12][3] MAIN[11][0] MAIN[10][7] MAIN[11][4] MAIN[10][3] MAIN[12][4] IMUX_DATA[12]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[13]
Bits Destination
MAIN[9][48] MAIN[9][46] MAIN[9][47] MAIN[9][50] MAIN[8][51] MAIN[9][45] MAIN[8][50] MAIN[10][45] IMUX_DATA[13]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[14]
Bits Destination
MAIN[12][14] MAIN[12][16] MAIN[12][15] MAIN[11][14] MAIN[11][19] MAIN[10][17] MAIN[10][14] MAIN[12][17] IMUX_DATA[14]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[15]
Bits Destination
MAIN[9][60] MAIN[9][62] MAIN[9][61] MAIN[10][62] MAIN[8][63] MAIN[9][58] MAIN[8][58] MAIN[10][59] IMUX_DATA[15]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX_BOUNCE[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX_BOUNCE[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY_BOUNCE[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY_BOUNCE[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY_BOUNCE[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
Used with DCM_* tiles.
Cells: 1
spartan3 INT_DCM switchbox INT programmable inverters
Destination Source Bit
IMUX_CLK_OPTINV[1] IMUX_CLK[1] MAIN[5][37]
IMUX_CLK_OPTINV[2] IMUX_CLK[2] MAIN[5][16]
IMUX_CLK_OPTINV[3] IMUX_CLK[3] MAIN[5][47]
spartan3 INT_DCM switchbox INT muxes OMUX[0]
Bits Destination
MAIN[6][6] MAIN[6][7] MAIN[7][0] MAIN[7][7] MAIN[6][3] MAIN[7][4] MAIN[6][2] MAIN[6][5] OMUX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[1]
Bits Destination
MAIN[6][1] MAIN[6][0] MAIN[7][1] MAIN[7][6] MAIN[6][4] MAIN[7][3] MAIN[7][2] MAIN[7][5] OMUX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[2]
Bits Destination
MAIN[6][9] MAIN[6][8] MAIN[7][15] MAIN[7][8] MAIN[6][12] MAIN[7][11] MAIN[6][13] MAIN[6][10] OMUX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[3]
Bits Destination
MAIN[6][14] MAIN[6][15] MAIN[7][14] MAIN[7][9] MAIN[6][11] MAIN[7][12] MAIN[7][13] MAIN[7][10] OMUX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[4]
Bits Destination
MAIN[6][22] MAIN[6][23] MAIN[7][16] MAIN[7][23] MAIN[6][19] MAIN[7][20] MAIN[6][18] MAIN[6][21] OMUX[4]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[5]
Bits Destination
MAIN[6][17] MAIN[6][16] MAIN[7][17] MAIN[7][22] MAIN[6][20] MAIN[7][19] MAIN[7][18] MAIN[7][21] OMUX[5]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[6]
Bits Destination
MAIN[6][25] MAIN[6][24] MAIN[7][31] MAIN[7][24] MAIN[6][28] MAIN[7][27] MAIN[6][29] MAIN[6][26] OMUX[6]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[7]
Bits Destination
MAIN[6][30] MAIN[6][31] MAIN[7][30] MAIN[7][25] MAIN[6][27] MAIN[7][28] MAIN[7][29] MAIN[7][26] OMUX[7]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[8]
Bits Destination
MAIN[6][38] MAIN[6][39] MAIN[7][32] MAIN[7][39] MAIN[6][35] MAIN[7][36] MAIN[6][34] MAIN[6][37] OMUX[8]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[9]
Bits Destination
MAIN[6][33] MAIN[6][32] MAIN[7][33] MAIN[7][38] MAIN[6][36] MAIN[7][35] MAIN[7][34] MAIN[7][37] OMUX[9]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[10]
Bits Destination
MAIN[6][41] MAIN[6][40] MAIN[7][47] MAIN[7][40] MAIN[6][44] MAIN[7][43] MAIN[6][45] MAIN[6][42] OMUX[10]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[11]
Bits Destination
MAIN[6][46] MAIN[6][47] MAIN[7][46] MAIN[7][41] MAIN[6][43] MAIN[7][44] MAIN[7][45] MAIN[7][42] OMUX[11]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[12]
Bits Destination
MAIN[6][54] MAIN[6][55] MAIN[7][48] MAIN[7][55] MAIN[6][51] MAIN[7][52] MAIN[6][50] MAIN[6][53] OMUX[12]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[13]
Bits Destination
MAIN[6][49] MAIN[6][48] MAIN[7][49] MAIN[7][54] MAIN[6][52] MAIN[7][51] MAIN[7][50] MAIN[7][53] OMUX[13]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[14]
Bits Destination
MAIN[6][57] MAIN[6][56] MAIN[7][63] MAIN[7][56] MAIN[6][60] MAIN[7][59] MAIN[6][61] MAIN[6][58] OMUX[14]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[15]
Bits Destination
MAIN[6][62] MAIN[6][63] MAIN[7][62] MAIN[7][57] MAIN[6][59] MAIN[7][60] MAIN[7][61] MAIN[7][58] OMUX[15]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OUT_FAN[4]
0 0 0 0 0 0 1 0 OUT_FAN[1]
0 0 0 0 0 1 0 0 OUT_FAN[2]
0 0 0 0 1 0 0 0 OUT_FAN[3]
0 0 0 1 0 0 0 0 OUT_FAN[5]
0 0 1 0 0 0 0 0 OUT_SEC[8]
0 1 0 0 0 0 0 1 OUT_FAN[0]
0 1 0 0 0 0 1 0 OUT_SEC[5]
0 1 0 0 0 1 0 0 OUT_SEC[6]
0 1 0 0 1 0 0 0 OUT_SEC[7]
0 1 0 1 0 0 0 0 OUT_SEC[9]
0 1 1 0 0 0 0 0 OUT_SEC[4]
1 0 0 0 0 0 0 1 OUT_SEC[2]
1 0 0 0 0 0 1 0 OUT_SEC[10]
1 0 0 0 0 1 0 0 OUT_SEC[0]
1 0 0 0 1 0 0 0 OUT_SEC[1]
1 0 0 1 0 0 0 0 OUT_SEC[3]
1 0 1 0 0 0 0 0 OUT_FAN[6]
1 1 0 0 0 0 0 1 OUT_SEC[14]
1 1 0 0 0 0 1 0 OUT_SEC[11]
1 1 0 0 0 1 0 0 OUT_SEC[12]
1 1 0 0 1 0 0 0 OUT_SEC[13]
1 1 0 1 0 0 0 0 OUT_SEC[15]
1 1 1 0 0 0 0 0 OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_DCM switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_DCM switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_DCM switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_DCM switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_DCM switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[0]
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[6]
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_DCM switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 OUT_FAN[3]
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 OUT_FAN[4]
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_DCM switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 0 1 0 0 0 OUT_FAN[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 OUT_FAN[5]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_DCM switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OUT_FAN[3]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 0 1 0 0 0 OUT_FAN[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 OUT_FAN[2]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_DCM switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 OUT_FAN[6]
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_DCM switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 0 1 0 0 0 OUT_FAN[1]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 OUT_FAN[7]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_DCM switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_DCM switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_DCM switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_DCM switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_DCM switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_DCM switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_DCM switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_DCM switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_DCM switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[3]
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_DCM switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 OUT_FAN[2]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 0 1 0 0 OUT_FAN[4]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_DCM switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OUT_FAN[5]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_DCM switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 0 1 0 0 OUT_FAN[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_DCM switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 0 1 0 OUT_FAN[5]
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 OUT_FAN[2]
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_DCM switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 OUT_FAN[1]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 0 1 0 0 OUT_FAN[6]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_DCM switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 0 1 0 OUT_FAN[0]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 OUT_FAN[7]
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_DCM switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OUT_FAN[6]
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_W0[1]
Bits Destination
MAIN[16][12] MAIN[16][13] MAIN[17][15] MAIN[17][14] MAIN[18][12] HEX_W0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_W1
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_W6_N[7]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_W6[1]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes HEX_W0[3]
Bits Destination
MAIN[16][28] MAIN[16][29] MAIN[17][31] MAIN[17][30] MAIN[18][28] HEX_W0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_W6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_W6[3]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_W0[4]
Bits Destination
MAIN[17][36] MAIN[17][37] MAIN[18][37] MAIN[16][39] MAIN[16][38] HEX_W0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_W6[2]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_W6[4]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_W0[5]
Bits Destination
MAIN[16][44] MAIN[16][45] MAIN[17][47] MAIN[17][46] MAIN[18][44] HEX_W0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_W6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_W6[5]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[0]
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 OUT_FAN[6]
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_DCM switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 0 1 0 0 OUT_FAN[3]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_E0[1]
Bits Destination
MAIN[17][12] MAIN[17][13] MAIN[18][13] MAIN[16][15] MAIN[16][14] HEX_E0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_N6[0]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_S4
0 1 0 1 0 HEX_S3[1]
0 1 1 0 0 OUT_FAN[5]
1 0 0 0 1 HEX_E6[1]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[1]
1 1 0 0 1 HEX_E6[3]
1 1 0 1 0 HEX_S6[3]
1 1 1 0 0 LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 0 1 OUT_FAN[3]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes HEX_E0[3]
Bits Destination
MAIN[17][28] MAIN[17][29] MAIN[18][29] MAIN[16][31] MAIN[16][30] HEX_E0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_N6[2]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_S3[3]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_E6[3]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[3]
1 1 0 0 1 HEX_E6[5]
1 1 0 1 0 HEX_S6[5]
1 1 1 0 0 LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_E0[4]
Bits Destination
MAIN[16][36] MAIN[16][37] MAIN[17][39] MAIN[17][38] MAIN[18][36] HEX_E0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_S6[6]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 HEX_N6[3]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_E6[4]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[4]
1 1 0 0 1 HEX_E6[6]
1 1 0 1 0 HEX_S3[4]
1 1 1 0 0 LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 OUT_FAN[0]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_DCM switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_DCM switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_DCM switchbox INT muxes HEX_S0[3]
Bits Destination
MAIN[17][27] MAIN[17][26] MAIN[18][26] MAIN[16][24] MAIN[16][25] HEX_S0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_W6
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX[6]
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_S6[5]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_S6[3]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_S0[4]
Bits Destination
MAIN[16][35] MAIN[16][34] MAIN[17][32] MAIN[17][33] MAIN[18][35] HEX_S0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_S6[6]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[4]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_S0[5]
Bits Destination
MAIN[17][43] MAIN[17][42] MAIN[18][42] MAIN[16][40] MAIN[16][41] HEX_S0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S3
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_E8
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_S6[7]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_S6[5]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_S0[6]
Bits Destination
MAIN[16][51] MAIN[16][50] MAIN[17][48] MAIN[17][49] MAIN[18][51] HEX_S0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_SW5
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_S7[0]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[6]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[3]
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_DCM switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 0 1 0 0 OUT_FAN[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[4]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 0 1 OUT_FAN[5]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_DCM switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 0 1 0 0 OUT_FAN[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[3]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_N0[4]
Bits Destination
MAIN[17][35] MAIN[17][34] MAIN[18][34] MAIN[16][32] MAIN[16][33] HEX_N0[4]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E7
0 0 0 1 0 HEX_W6[2]
0 0 1 0 0 OUT_FAN[5]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_W3[4]
0 1 1 0 0 OUT_FAN[2]
1 0 0 0 1 HEX_N6[4]
1 0 0 1 0 HEX_E6[5]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[2]
1 1 0 1 0 HEX_E3[4]
1 1 1 0 0 LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 0 1 0 0 OUT_FAN[1]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
0 1 1 0 0 OUT_FAN[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_N0[6]
Bits Destination
MAIN[17][51] MAIN[17][50] MAIN[18][50] MAIN[16][48] MAIN[16][49] HEX_N0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 0 1 0 HEX_W6[4]
0 0 1 0 0 OUT_FAN[0]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 HEX_W3[6]
0 1 1 0 0 OUT_FAN[7]
1 0 0 0 1 HEX_N6[6]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N6[4]
1 1 0 1 0 HEX_E3[6]
1 1 1 0 0 LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OUT_FAN[6]
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_DCM switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][36] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[4][32] MAIN[4][33] MAIN[4][34] MAIN[4][35] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 GCLK[0]
0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 GCLK[1]
0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 GCLK[2]
0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 GCLK[3]
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 DBL_E1[4]
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 DBL_E0[4]
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 GCLK[4]
0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 GCLK[5]
0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 GCLK[6]
0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 GCLK[7]
0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 DBL_W1[4]
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 DBL_W2[4]
0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 DCM_CLKPAD[0]
0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 DCM_CLKPAD[1]
0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 DCM_CLKPAD[2]
0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 DCM_CLKPAD[3]
0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 HEX_N5[4]
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 HEX_S4[4]
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HEX_N2[4]
spartan3 INT_DCM switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[5][27] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[5][31] MAIN[5][30] MAIN[5][29] MAIN[5][28] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 GCLK[0]
0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 GCLK[1]
0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 GCLK[2]
0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 GCLK[3]
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 DBL_E1[3]
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 DBL_E0[3]
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 GCLK[4]
0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 GCLK[5]
0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 GCLK[6]
0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 GCLK[7]
0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 DBL_W1[3]
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 DBL_W2[3]
0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 DCM_CLKPAD[0]
0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 DCM_CLKPAD[1]
0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 DCM_CLKPAD[2]
0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 DCM_CLKPAD[3]
0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 HEX_N5[4]
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 HEX_S4[4]
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HEX_N2[4]
spartan3 INT_DCM switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[5][36] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[5][32] MAIN[5][33] MAIN[5][34] MAIN[5][35] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 GCLK[0]
0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 GCLK[1]
0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 GCLK[2]
0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 GCLK[3]
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 DBL_E1[4]
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 DBL_E0[4]
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 GCLK[4]
0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 GCLK[5]
0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 GCLK[6]
0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 GCLK[7]
0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 DBL_W1[4]
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 DBL_W2[4]
0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 DCM_CLKPAD[0]
0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 DCM_CLKPAD[1]
0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 DCM_CLKPAD[2]
0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 DCM_CLKPAD[3]
0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 HEX_N5[4]
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 HEX_S4[4]
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HEX_N2[4]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 0 1 0 0 0 0 OUT_FAN[6]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 0 1 0 0 0 OUT_FAN[1]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
1 1 1 0 1 0 0 0 OUT_FAN[2]
1 1 1 1 0 0 0 0 OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 0 1 0 0 OUT_FAN[4]
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 0 1 0 0 0 OUT_FAN[3]
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 PULLUP
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 0 1 0 0 OUT_FAN[7]
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 0 0 1 0 0 0 0 OUT_FAN[0]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[12]
Bits Destination
MAIN[3][23] MAIN[3][22] MAIN[3][21] OUT_SEC[12]
Source
0 0 0 off
0 0 1 IMUX_DATA[31]
0 1 0 IMUX_DATA[23]
0 1 1 IMUX_CLK_OPTINV[3]
1 0 0 IMUX_DATA[19]
1 0 1 IMUX_DATA[3]
1 1 0 IMUX_DATA[27]
spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[13]
Bits Destination
MAIN[3][16] MAIN[3][18] MAIN[3][17] OUT_SEC[13]
Source
0 0 0 off
0 0 1 IMUX_DATA[22]
0 1 0 IMUX_DATA[30]
0 1 1 IMUX_CLK_OPTINV[2]
1 0 0 IMUX_DATA[18]
1 0 1 IMUX_DATA[26]
spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[14]
Bits Destination
MAIN[3][48] MAIN[3][49] MAIN[3][50] OUT_SEC[14]
Source
0 0 0 off
0 0 1 IMUX_DATA[29]
0 1 0 IMUX_DATA[21]
0 1 1 IMUX_CLK_OPTINV[1]
1 0 0 IMUX_DATA[17]
1 0 1 IMUX_DATA[2]
1 1 0 IMUX_DATA[25]
spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[15]
Bits Destination
MAIN[3][42] MAIN[3][41] MAIN[3][40] OUT_SEC[15]
Source
0 0 0 off
0 0 1 IMUX_DATA[16]
0 1 0 IMUX_DATA[20]
0 1 1 IMUX_DATA[24]
1 0 0 IMUX_DATA[28]
Used for the dummy interconnect tile in DCM holes on Spartan 3 devices with more than 2 BRAM columns. Not associated with any primitive.
Cells: 1
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[14][22] MAIN[13][20] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_W2[0]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_W2[2]
1 1 0 0 1 0 DBL_S1[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[14][54] MAIN[13][52] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_W2[4]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_W2[6]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[13][60] MAIN[14][62] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_W2[5]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_W2[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][21] MAIN[15][20] MAIN[15][22] MAIN[13][23] MAIN[13][22] MAIN[13][21] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 0 1 DBL_E2[2]
0 1 0 0 1 0 DBL_S2[4]
0 1 0 1 0 0 DBL_N2[1]
0 1 1 0 0 0 HEX_N3[2]
1 0 0 1 0 0 HEX_S6[3]
1 0 1 0 0 0 HEX_W6[2]
1 1 0 0 0 1 DBL_E2[4]
1 1 0 0 1 0 DBL_S1[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][2] MAIN[15][3] MAIN[13][0] MAIN[15][1] MAIN[13][1] MAIN[13][2] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 DBL_S2[2]
0 1 0 0 1 0 DBL_W1[0]
0 1 0 1 0 0 DBL_W2_N[6]
0 1 1 0 0 0 HEX_E3[0]
1 0 0 1 0 0 HEX_W6_N[7]
1 0 1 0 0 0 HEX_S6[0]
1 1 0 0 0 1 DBL_S2[0]
1 1 0 0 1 0 DBL_E1[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][17] MAIN[13][18] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W1[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_S2[2]
1 1 0 0 1 0 DBL_E1[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][26] MAIN[15][27] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 DBL_S2[5]
0 1 0 0 1 0 DBL_W1[3]
0 1 0 1 0 0 DBL_E2[4]
0 1 1 0 0 0 HEX_W3[3]
1 0 0 0 1 0 HEX_S6[3]
1 0 1 0 0 0 HEX_W6[2]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][57] MAIN[13][56] MAIN[13][58] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 0 1 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[1]
1 0 0 0 1 0 DBL_W1[7]
1 0 0 1 0 0 DBL_E2_S[0]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_S2[7]
1 1 0 0 1 0 DBL_W2[5]
1 1 0 1 0 0 DBL_E1[7]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[14][1] MAIN[13][3] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_N2[0]
1 0 0 0 1 0 DBL_W1[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_N3[6]
1 1 0 0 1 0 DBL_E1[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[14][17] MAIN[13][19] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 0 1 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_N2[2]
1 0 0 0 1 0 DBL_W1[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_N2[0]
1 1 0 0 1 0 DBL_E1[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][57] MAIN[14][56] MAIN[13][59] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N11
0 0 0 0 1 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_W9
0 1 0 0 1 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_N2[7]
1 0 0 0 1 0 DBL_W1[7]
1 0 0 1 0 0 DBL_E2_S[0]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_N2[5]
1 1 0 0 1 0 DBL_W2[5]
1 1 0 1 0 0 DBL_E1[7]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][0] MAIN[17][1] MAIN[18][3] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_W6_N[6]
0 1 0 1 0 HEX_W3[0]
1 0 0 0 1 HEX_S6[2]
1 0 0 1 0 HEX_E6[1]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_S6[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[18][58] MAIN[16][56] MAIN[16][57] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 0 1 0 HEX_E6_S[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_S7[1]
1 0 0 1 0 HEX_W3[7]
1 0 1 0 0 HEX_W6[5]
1 1 0 0 1 HEX_S6[7]
1 1 0 1 0 HEX_E3[7]
1 1 1 0 0 LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[18][2] MAIN[16][0] MAIN[16][1] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_W6_N[6]
0 1 0 0 1 OMUX_N9
0 1 0 1 0 HEX_W3[0]
1 0 0 0 1 HEX_N6[0]
1 0 0 1 0 HEX_E6[1]
1 0 1 0 0 LV[0]
1 1 0 0 1 HEX_N7[6]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][0] MAIN[18][1] MAIN[18][6] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_E2
0 0 0 1 0 HEX_E6[0]
0 0 1 0 0 HEX_E5[0]
0 1 0 0 1 DBL_E1[2]
0 1 0 1 0 HEX_E2[0]
1 0 1 0 0 HEX_E1[0]
1 1 0 0 1 HEX_E3[0]
1 1 0 1 0 DBL_W1[1]
1 1 1 0 0 HEX_E4[0]
Used for the dummy interconnect tile in DCM holes on Spartan 3E devices with 2 DCMs. Not associated with any primitive.
Cells: 1
spartan3 INT_DCM_S3E_DUMMY switchbox INT programmable inverters
Destination Source Bit
IMUX_CLK_OPTINV[1] IMUX_CLK[1] MAIN[5][37]
IMUX_CLK_OPTINV[2] IMUX_CLK[2] MAIN[5][16]
IMUX_CLK_OPTINV[3] IMUX_CLK[3] MAIN[5][47]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[0]
Bits Destination
MAIN[14][4] MAIN[14][5] MAIN[15][7] MAIN[14][7] MAIN[14][6] MAIN[13][4] DBL_W0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S0
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_NW10
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_W2_N[6]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_W2[0]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[1]
Bits Destination
MAIN[14][12] MAIN[14][13] MAIN[14][14] MAIN[15][15] MAIN[14][15] MAIN[13][12] DBL_W0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_W1
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
1 0 0 0 0 1 DBL_W2_N[7]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_W2[1]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[2]
Bits Destination
MAIN[14][20] MAIN[14][21] MAIN[15][23] MAIN[14][23] MAIN[13][20] MAIN[14][22] DBL_W0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX_WN14
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_W2[0]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_W2[2]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[3]
Bits Destination
MAIN[14][28] MAIN[14][29] MAIN[14][30] MAIN[15][31] MAIN[14][31] MAIN[13][28] DBL_W0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_W2[1]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_W2[3]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[4]
Bits Destination
MAIN[14][36] MAIN[14][37] MAIN[15][39] MAIN[14][39] MAIN[14][38] MAIN[13][36] DBL_W0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_N12
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_W2[2]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_W2[4]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[5]
Bits Destination
MAIN[14][44] MAIN[14][45] MAIN[14][46] MAIN[15][47] MAIN[14][47] MAIN[13][44] DBL_W0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_W2[3]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_W2[5]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[6]
Bits Destination
MAIN[14][52] MAIN[14][53] MAIN[15][55] MAIN[14][55] MAIN[13][52] MAIN[14][54] DBL_W0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_SW5
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W2[4]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_S1[6]
1 1 0 0 1 0 DBL_W2[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[7]
Bits Destination
MAIN[14][60] MAIN[14][61] MAIN[15][63] MAIN[14][63] MAIN[14][62] MAIN[13][60] DBL_W0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[9]
0 1 0 0 1 0 OMUX_S0
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 DBL_W2[5]
1 0 0 0 1 0 HEX_N3[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 DBL_W2[7]
1 1 0 0 1 0 HEX_S3[7]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[0]
Bits Destination
MAIN[15][4] MAIN[15][5] MAIN[15][6] MAIN[13][7] MAIN[13][6] MAIN[13][5] DBL_E0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 1 0 0 HEX_E6[0]
0 0 1 0 0 0 HEX_N6[0]
0 1 0 0 0 1 OMUX_E2
0 1 0 1 0 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_E2[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_N3[7]
1 0 1 0 0 0 HEX_N3[0]
1 1 0 0 0 1 DBL_E2[2]
1 1 0 0 1 0 DBL_S1[0]
1 1 0 1 0 0 DBL_N1[0]
1 1 1 0 0 0 HEX_S3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[1]
Bits Destination
MAIN[15][12] MAIN[15][13] MAIN[13][14] MAIN[15][14] MAIN[13][15] MAIN[13][13] DBL_E0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 0 1 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_S4
0 1 0 0 1 0 HEX_S6[2]
0 1 0 1 0 0 HEX_W6[1]
1 0 0 0 0 1 DBL_E2[1]
1 0 0 0 1 0 DBL_S1[1]
1 0 0 1 0 0 DBL_N2[0]
1 0 1 0 0 0 HEX_N3[1]
1 1 0 0 0 1 DBL_E2[3]
1 1 0 0 1 0 DBL_S2[3]
1 1 0 1 0 0 DBL_N1[1]
1 1 1 0 0 0 HEX_S3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[2]
Bits Destination
MAIN[15][20] MAIN[15][21] MAIN[15][22] MAIN[13][23] MAIN[13][21] MAIN[13][22] DBL_E0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_E6[2]
0 0 1 0 0 0 HEX_N6[2]
0 1 0 0 1 0 OMUX[6]
0 1 0 1 0 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[4]
1 0 0 0 1 0 DBL_E2[2]
1 0 0 1 0 0 DBL_N2[1]
1 0 1 0 0 0 HEX_N3[2]
1 1 0 0 0 1 DBL_S1[2]
1 1 0 0 1 0 DBL_E2[4]
1 1 0 1 0 0 DBL_N1[2]
1 1 1 0 0 0 HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[3]
Bits Destination
MAIN[15][28] MAIN[15][29] MAIN[13][30] MAIN[15][30] MAIN[13][31] MAIN[13][29] DBL_E0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 0 1 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 HEX_S6[4]
0 1 0 1 0 0 HEX_W6[3]
1 0 0 0 0 1 DBL_E2[3]
1 0 0 0 1 0 DBL_S1[3]
1 0 0 1 0 0 DBL_N2[2]
1 0 1 0 0 0 HEX_N3[3]
1 1 0 0 0 1 DBL_E2[5]
1 1 0 0 1 0 DBL_S2[5]
1 1 0 1 0 0 DBL_N1[3]
1 1 1 0 0 0 HEX_S3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[4]
Bits Destination
MAIN[15][36] MAIN[15][37] MAIN[15][38] MAIN[13][39] MAIN[13][38] MAIN[13][37] DBL_E0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 1 0 0 HEX_E6[4]
0 0 1 0 0 0 HEX_N6[4]
0 1 0 0 0 1 OMUX_E8
0 1 0 1 0 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_E2[4]
1 0 0 0 1 0 DBL_S2[6]
1 0 0 1 0 0 DBL_N2[3]
1 0 1 0 0 0 HEX_N3[4]
1 1 0 0 0 1 DBL_E2[6]
1 1 0 0 1 0 DBL_S1[4]
1 1 0 1 0 0 DBL_N1[4]
1 1 1 0 0 0 HEX_S3[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[5]
Bits Destination
MAIN[15][44] MAIN[15][45] MAIN[13][46] MAIN[15][46] MAIN[13][47] MAIN[13][45] DBL_E0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 0 1 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_ES7
0 1 0 0 1 0 HEX_S6[6]
0 1 0 1 0 0 HEX_W6[5]
1 0 0 0 0 1 DBL_E2[5]
1 0 0 0 1 0 DBL_S1[5]
1 0 0 1 0 0 DBL_N2[4]
1 0 1 0 0 0 HEX_N3[5]
1 1 0 0 0 1 DBL_E2[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_N1[5]
1 1 1 0 0 0 HEX_S3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[6]
Bits Destination
MAIN[15][52] MAIN[15][53] MAIN[15][54] MAIN[13][55] MAIN[13][54] MAIN[13][53] DBL_E0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 1 0 0 HEX_E6[6]
0 0 1 0 0 0 HEX_N6[6]
0 1 0 0 0 1 OMUX_SE3
0 1 0 0 1 0 OMUX[11]
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2[6]
1 0 0 0 1 0 DBL_S3[0]
1 0 0 1 0 0 DBL_N2[5]
1 0 1 0 0 0 HEX_N3[6]
1 1 0 0 0 1 DBL_E2_S[0]
1 1 0 0 1 0 DBL_S1[6]
1 1 0 1 0 0 DBL_N1[6]
1 1 1 0 0 0 HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[7]
Bits Destination
MAIN[15][60] MAIN[15][61] MAIN[15][62] MAIN[13][63] MAIN[13][61] MAIN[13][62] DBL_E0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX_S0
0 1 0 0 1 0 OMUX_S2
0 1 0 1 0 0 HEX_S7[0]
0 1 1 0 0 0 HEX_W6[7]
1 0 0 0 0 1 HEX_N3[7]
1 0 0 0 1 0 DBL_E2[7]
1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 0 0 DBL_N2[6]
1 1 0 0 0 1 HEX_S3[7]
1 1 0 0 1 0 DBL_E2_S[1]
1 1 0 1 0 0 DBL_S3[1]
1 1 1 0 0 0 DBL_N1[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[0]
Bits Destination
MAIN[15][3] MAIN[15][2] MAIN[13][0] MAIN[15][1] MAIN[13][2] MAIN[13][1] DBL_S0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_S0
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX[2]
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_S2[2]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_S2[0]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[1]
Bits Destination
MAIN[15][11] MAIN[15][10] MAIN[15][9] MAIN[13][9] MAIN[13][8] MAIN[13][10] DBL_S0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[2]
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_E2
0 1 0 0 1 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_S2[3]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_S2[1]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[2]
Bits Destination
MAIN[15][19] MAIN[15][18] MAIN[13][16] MAIN[15][17] MAIN[13][18] MAIN[13][17] DBL_S0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX[6]
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 1 0 OMUX_S4
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_S2[4]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_S2[2]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[3]
Bits Destination
MAIN[15][27] MAIN[15][26] MAIN[15][25] MAIN[13][25] MAIN[13][24] MAIN[13][26] DBL_S0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_W6
0 0 0 0 1 0 HEX_E6[3]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX[6]
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_S2[5]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_S2[3]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[4]
Bits Destination
MAIN[15][35] MAIN[15][34] MAIN[13][32] MAIN[15][33] MAIN[13][33] MAIN[13][34] DBL_S0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_WS1
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_SE3
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_S2[6]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_S2[4]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[5]
Bits Destination
MAIN[15][43] MAIN[15][42] MAIN[15][41] MAIN[13][41] MAIN[13][40] MAIN[13][42] DBL_S0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_S3
0 0 0 0 1 0 HEX_E6[5]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_E8
0 1 0 0 1 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_S2[7]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_S2[5]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[6]
Bits Destination
MAIN[15][51] MAIN[15][50] MAIN[13][48] MAIN[15][49] MAIN[13][49] MAIN[13][50] DBL_S0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_SW5
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_ES7
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_S3[0]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_S2[6]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[7]
Bits Destination
MAIN[15][59] MAIN[15][58] MAIN[15][57] MAIN[13][56] MAIN[13][58] MAIN[13][57] DBL_S0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_WS1
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_SE3
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_S3[1]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_S2[7]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[0]
Bits Destination
MAIN[14][3] MAIN[14][2] MAIN[14][0] MAIN[15][0] MAIN[13][3] MAIN[14][1] DBL_N0[0]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_EN8
0 0 0 1 0 0 HEX_N6[0]
0 0 1 0 0 0 HEX_E6[0]
0 1 0 0 0 1 OMUX[0]
0 1 0 0 1 0 OMUX_N9
0 1 0 1 0 0 HEX_W6_N[7]
0 1 1 0 0 0 HEX_S6[0]
1 0 0 0 0 1 DBL_W1[0]
1 0 0 0 1 0 DBL_N2[0]
1 0 0 1 0 0 DBL_W2_N[6]
1 0 1 0 0 0 HEX_E3[0]
1 1 0 0 0 1 DBL_E1[0]
1 1 0 0 1 0 DBL_N3[6]
1 1 0 1 0 0 HEX_W3[0]
1 1 1 0 0 0 DBL_E2[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[1]
Bits Destination
MAIN[14][11] MAIN[14][10] MAIN[15][8] MAIN[14][9] MAIN[14][8] MAIN[13][11] DBL_N0[1]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_N10
0 0 0 0 1 0 HEX_E6[1]
0 0 1 0 0 0 HEX_N6[1]
0 1 0 0 0 1 OMUX_NW10
0 1 0 0 1 0 HEX_S6[1]
0 1 1 0 0 0 HEX_W6[0]
1 0 0 0 0 1 DBL_N2[1]
1 0 0 0 1 0 DBL_W1[1]
1 0 0 1 0 0 DBL_E2[2]
1 0 1 0 0 0 HEX_W3[1]
1 1 0 0 0 1 DBL_N3[7]
1 1 0 0 1 0 DBL_W2_N[7]
1 1 0 1 0 0 DBL_E1[1]
1 1 1 0 0 0 HEX_E3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[2]
Bits Destination
MAIN[14][19] MAIN[14][18] MAIN[14][16] MAIN[15][16] MAIN[13][19] MAIN[14][17] DBL_N0[2]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[4]
0 0 0 0 1 0 OMUX_NE12
0 0 0 1 0 0 HEX_N6[2]
0 0 1 0 0 0 HEX_E6[2]
0 1 0 0 1 0 OMUX_W1
0 1 0 1 0 0 HEX_W6[1]
0 1 1 0 0 0 HEX_S6[2]
1 0 0 0 0 1 DBL_W1[2]
1 0 0 0 1 0 DBL_N2[2]
1 0 0 1 0 0 DBL_W2[0]
1 0 1 0 0 0 HEX_E3[2]
1 1 0 0 0 1 DBL_E1[2]
1 1 0 0 1 0 DBL_N2[0]
1 1 0 1 0 0 HEX_W3[2]
1 1 1 0 0 0 DBL_E2[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[3]
Bits Destination
MAIN[14][27] MAIN[14][26] MAIN[15][24] MAIN[14][25] MAIN[14][24] MAIN[13][27] DBL_N0[3]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_EN8
0 0 0 0 1 0 HEX_E6[3]
0 0 1 0 0 0 HEX_N6[3]
0 1 0 0 0 1 OMUX_WN14
0 1 0 0 1 0 HEX_S6[3]
0 1 1 0 0 0 HEX_W6[2]
1 0 0 0 0 1 DBL_N2[3]
1 0 0 0 1 0 DBL_W1[3]
1 0 0 1 0 0 DBL_E2[4]
1 0 1 0 0 0 HEX_W3[3]
1 1 0 0 0 1 DBL_N2[1]
1 1 0 0 1 0 DBL_W2[1]
1 1 0 1 0 0 DBL_E1[3]
1 1 1 0 0 0 HEX_E3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[4]
Bits Destination
MAIN[14][35] MAIN[14][34] MAIN[14][32] MAIN[15][32] MAIN[14][33] MAIN[13][35] DBL_N0[4]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_E7
0 0 0 1 0 0 HEX_N6[4]
0 0 1 0 0 0 HEX_E6[4]
0 1 0 0 0 1 OMUX_NW10
0 1 0 1 0 0 HEX_W6[3]
0 1 1 0 0 0 HEX_S6[4]
1 0 0 0 0 1 DBL_N2[4]
1 0 0 0 1 0 DBL_W1[4]
1 0 0 1 0 0 DBL_W2[2]
1 0 1 0 0 0 HEX_E3[4]
1 1 0 0 0 1 DBL_N2[2]
1 1 0 0 1 0 DBL_E1[4]
1 1 0 1 0 0 HEX_W3[4]
1 1 1 0 0 0 DBL_E2[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[5]
Bits Destination
MAIN[14][43] MAIN[14][42] MAIN[15][40] MAIN[14][41] MAIN[14][40] MAIN[13][43] DBL_N0[5]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX_NE12
0 0 0 0 1 0 HEX_E6[5]
0 0 1 0 0 0 HEX_N6[5]
0 1 0 0 0 1 OMUX_N12
0 1 0 0 1 0 HEX_S6[5]
0 1 1 0 0 0 HEX_W6[4]
1 0 0 0 0 1 DBL_N2[5]
1 0 0 0 1 0 DBL_W1[5]
1 0 0 1 0 0 DBL_E2[6]
1 0 1 0 0 0 HEX_W3[5]
1 1 0 0 0 1 DBL_N2[3]
1 1 0 0 1 0 DBL_W2[3]
1 1 0 1 0 0 DBL_E1[5]
1 1 1 0 0 0 HEX_E3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[6]
Bits Destination
MAIN[14][51] MAIN[14][50] MAIN[14][48] MAIN[15][48] MAIN[14][49] MAIN[13][51] DBL_N0[6]
Source
0 0 0 0 0 0 off
0 0 0 0 0 1 OMUX[9]
0 0 0 1 0 0 HEX_N6[6]
0 0 1 0 0 0 HEX_E6[6]
0 1 0 0 0 1 OMUX_WN14
0 1 0 1 0 0 HEX_W6[5]
0 1 1 0 0 0 HEX_S6[6]
1 0 0 0 0 1 DBL_N2[6]
1 0 0 0 1 0 DBL_W1[6]
1 0 0 1 0 0 DBL_W2[4]
1 0 1 0 0 0 HEX_E3[6]
1 1 0 0 0 1 DBL_N2[4]
1 1 0 0 1 0 DBL_E1[6]
1 1 0 1 0 0 HEX_W3[6]
1 1 1 0 0 0 DBL_E2[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[7]
Bits Destination
MAIN[14][59] MAIN[14][58] MAIN[15][56] MAIN[14][56] MAIN[13][59] MAIN[14][57] DBL_N0[7]
Source
0 0 0 0 0 0 off
0 0 0 0 1 0 OMUX_N11
0 0 0 1 0 0 HEX_E6[7]
0 0 1 0 0 0 HEX_N6[7]
0 1 0 0 0 1 OMUX[11]
0 1 0 0 1 0 OMUX_W9
0 1 0 1 0 0 HEX_S6[7]
0 1 1 0 0 0 HEX_W6[6]
1 0 0 0 0 1 DBL_E2_S[0]
1 0 0 0 1 0 DBL_N2[7]
1 0 0 1 0 0 DBL_W1[7]
1 0 1 0 0 0 HEX_W3[7]
1 1 0 0 0 1 DBL_E1[7]
1 1 0 0 1 0 DBL_N2[5]
1 1 0 1 0 0 DBL_W2[5]
1 1 1 0 0 0 HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[0]
Bits Destination
MAIN[17][4] MAIN[17][5] MAIN[18][5] MAIN[16][7] MAIN[16][6] HEX_W0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_S0
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 HEX_N7[7]
1 0 0 0 1 HEX_W6_N[6]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_W6[0]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[2]
Bits Destination
MAIN[17][20] MAIN[17][21] MAIN[16][23] MAIN[16][22] MAIN[18][21] HEX_W0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_S6[4]
0 1 0 1 0 OMUX_WN14
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_W6[0]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[2]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[6]
Bits Destination
MAIN[17][52] MAIN[17][53] MAIN[16][55] MAIN[16][54] MAIN[18][53] HEX_W0[6]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_SW5
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_N3[6]
1 0 0 1 0 HEX_W6[4]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_W6[6]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[7]
Bits Destination
MAIN[16][60] MAIN[16][61] MAIN[17][62] MAIN[17][63] MAIN[18][60] HEX_W0[7]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_WS1
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX[9]
0 1 0 1 0 OMUX_S0
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N3[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 HEX_W6[7]
1 1 0 1 0 LH[12]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[0]
Bits Destination
MAIN[16][4] MAIN[16][5] MAIN[17][7] MAIN[17][6] MAIN[18][4] HEX_E0[0]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_S6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 HEX_N7[7]
1 0 0 0 1 HEX_E6[0]
1 0 0 1 0 LH[6]
1 0 1 0 0 HEX_N3[0]
1 1 0 0 1 HEX_E6[2]
1 1 0 1 0 HEX_S3[0]
1 1 1 0 0 LH[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[2]
Bits Destination
MAIN[16][20] MAIN[16][21] MAIN[17][22] MAIN[18][20] MAIN[17][23] HEX_E0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_S6[4]
0 1 0 1 0 OMUX[6]
0 1 1 0 0 HEX_N6[1]
1 0 0 0 1 HEX_N3[2]
1 0 0 1 0 HEX_E6[2]
1 0 1 0 0 LH[6]
1 1 0 0 1 LH[18]
1 1 0 1 0 HEX_E6[4]
1 1 1 0 0 HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[5]
Bits Destination
MAIN[17][44] MAIN[17][45] MAIN[18][45] MAIN[16][47] MAIN[16][46] HEX_E0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_N6[4]
0 1 0 0 1 OMUX_ES7
0 1 0 1 0 HEX_S3[5]
1 0 0 0 1 HEX_E6[5]
1 0 0 1 0 LH[0]
1 0 1 0 0 HEX_N3[5]
1 1 0 0 1 HEX_E6[7]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 LH[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[6]
Bits Destination
MAIN[16][52] MAIN[16][53] MAIN[17][54] MAIN[17][55] MAIN[18][52] HEX_E0[6]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[9]
0 0 1 0 0 HEX_S7[0]
0 1 0 0 1 OMUX_SE3
0 1 0 1 0 OMUX[11]
0 1 1 0 0 HEX_N6[5]
1 0 0 0 1 HEX_E6[6]
1 0 0 1 0 HEX_N3[6]
1 0 1 0 0 LH[6]
1 1 0 0 1 HEX_E6_S[0]
1 1 0 1 0 LH[18]
1 1 1 0 0 HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[7]
Bits Destination
MAIN[17][60] MAIN[17][61] MAIN[16][63] MAIN[16][62] MAIN[18][61] HEX_E0[7]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_N6[6]
0 1 0 0 1 OMUX_S0
0 1 0 1 0 OMUX_S2
0 1 1 0 0 HEX_S3[7]
1 0 0 0 1 HEX_N3[7]
1 0 0 1 0 HEX_E6[7]
1 0 1 0 0 LH[0]
1 1 0 0 1 LH[12]
1 1 0 1 0 HEX_E6_S[1]
1 1 1 0 0 HEX_S7[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[0]
Bits Destination
MAIN[16][3] MAIN[16][2] MAIN[17][1] MAIN[18][3] MAIN[17][0] HEX_S0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_S0
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX[2]
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[2]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[0]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[1]
Bits Destination
MAIN[17][11] MAIN[17][10] MAIN[18][10] MAIN[16][8] MAIN[16][9] HEX_S0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[2]
0 0 0 1 0 HEX_E6[2]
0 1 0 0 1 OMUX_E2
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_S6[3]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_S6[1]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[2]
Bits Destination
MAIN[16][19] MAIN[16][18] MAIN[17][17] MAIN[18][19] MAIN[17][16] HEX_S0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX[6]
0 0 1 0 0 HEX_W6[0]
0 1 0 1 0 OMUX_S4
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_S6[4]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_S6[2]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[7]
Bits Destination
MAIN[17][59] MAIN[17][58] MAIN[16][56] MAIN[16][57] MAIN[18][58] HEX_S0[7]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_WS1
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_SE3
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_S7[1]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_S6[7]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[0]
Bits Destination
MAIN[17][3] MAIN[17][2] MAIN[16][0] MAIN[16][1] MAIN[18][2] HEX_N0[0]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_EN8
0 0 1 0 0 HEX_W6_N[6]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 OMUX_N9
0 1 1 0 0 HEX_W3[0]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[0]
1 0 1 0 0 HEX_E6[1]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N7[6]
1 1 1 0 0 HEX_E3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[1]
Bits Destination
MAIN[16][11] MAIN[16][10] MAIN[17][8] MAIN[17][9] MAIN[18][11] HEX_N0[1]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_N10
0 0 0 1 0 HEX_E6[2]
0 1 0 0 1 OMUX_NW10
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_N6[1]
1 0 0 1 0 HEX_W3[1]
1 0 1 0 0 HEX_W6_N[7]
1 1 0 0 1 HEX_N7[7]
1 1 0 1 0 HEX_E3[1]
1 1 1 0 0 LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[2]
Bits Destination
MAIN[17][19] MAIN[17][18] MAIN[16][16] MAIN[16][17] MAIN[18][18] HEX_N0[2]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX[4]
0 0 0 1 0 OMUX_NE12
0 0 1 0 0 HEX_W6[0]
0 1 0 1 0 OMUX_W1
0 1 1 0 0 HEX_W3[2]
1 0 0 0 1 LV[0]
1 0 0 1 0 HEX_N6[2]
1 0 1 0 0 HEX_E6[3]
1 1 0 0 1 LV[12]
1 1 0 1 0 HEX_N6[0]
1 1 1 0 0 HEX_E3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[3]
Bits Destination
MAIN[16][27] MAIN[16][26] MAIN[17][24] MAIN[17][25] MAIN[18][27] HEX_N0[3]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_EN8
0 0 0 1 0 HEX_E6[4]
0 1 0 0 1 OMUX_WN14
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_N6[3]
1 0 0 1 0 HEX_W3[3]
1 0 1 0 0 HEX_W6[1]
1 1 0 0 1 HEX_N6[1]
1 1 0 1 0 HEX_E3[3]
1 1 1 0 0 LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[5]
Bits Destination
MAIN[16][43] MAIN[16][42] MAIN[17][40] MAIN[17][41] MAIN[18][43] HEX_N0[5]
Source
0 0 0 0 0 off
0 0 0 0 1 OMUX_NE12
0 0 0 1 0 HEX_E6[6]
0 1 0 0 1 OMUX_N12
0 1 0 1 0 LV[6]
1 0 0 0 1 HEX_N6[5]
1 0 0 1 0 HEX_W3[5]
1 0 1 0 0 HEX_W6[3]
1 1 0 0 1 HEX_N6[3]
1 1 0 1 0 HEX_E3[5]
1 1 1 0 0 LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[7]
Bits Destination
MAIN[16][59] MAIN[16][58] MAIN[17][57] MAIN[18][59] MAIN[17][56] HEX_N0[7]
Source
0 0 0 0 0 off
0 0 0 1 0 OMUX_N11
0 0 1 0 0 HEX_E6_S[0]
0 1 0 0 1 OMUX[11]
0 1 0 1 0 OMUX_W9
0 1 1 0 0 LV[6]
1 0 0 0 1 HEX_W6[5]
1 0 0 1 0 HEX_N6[7]
1 0 1 0 0 HEX_W3[7]
1 1 0 0 1 LV[18]
1 1 0 1 0 HEX_N6[5]
1 1 1 0 0 HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LV[0]
Bits Destination
MAIN[18][8] MAIN[18][7] MAIN[18][1] MAIN[18][6] MAIN[18][0] LV[0]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LV[12]
Bits Destination
MAIN[18][9] MAIN[18][14] MAIN[18][16] MAIN[18][15] MAIN[18][17] LV[12]
Source
0 0 0 0 0 off
0 0 0 0 1 HEX_E5[0]
0 0 0 1 0 OMUX_E2
0 0 1 0 0 HEX_E6[0]
0 1 0 0 1 OMUX[0]
0 1 0 1 0 DBL_E1[2]
0 1 1 0 0 HEX_E2[0]
1 0 0 0 1 HEX_E1[0]
1 1 0 0 1 HEX_E4[0]
1 1 0 1 0 HEX_E3[0]
1 1 1 0 0 DBL_W1[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_CLK[1]
Bits Destination
MAIN[5][39] MAIN[5][38] MAIN[4][39] MAIN[4][37] MAIN[4][42] MAIN[4][40] MAIN[5][40] MAIN[4][43] MAIN[4][47] MAIN[5][44] IMUX_CLK[1]
Source
0 0 0 0 0 0 0 0 0 0 off
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_CLK[2]
Bits Destination
MAIN[5][17] MAIN[5][18] MAIN[4][18] MAIN[4][17] MAIN[5][22] MAIN[4][22] MAIN[4][25] MAIN[5][21] MAIN[5][20] MAIN[4][19] IMUX_CLK[2]
Source
0 0 0 0 0 0 0 0 0 0 off
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[3]
0 0 0 1 1 0 0 0 0 0 DBL_E0[3]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[3]
0 0 1 0 1 0 0 0 0 0 DBL_W2[3]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_CLK[3]
Bits Destination
MAIN[5][46] MAIN[5][45] MAIN[4][45] MAIN[4][46] MAIN[5][41] MAIN[4][41] MAIN[4][38] MAIN[5][42] MAIN[5][43] MAIN[4][44] IMUX_CLK[3]
Source
0 0 0 0 0 0 0 0 0 0 off
0 0 0 1 0 0 0 0 0 1 GCLK[0]
0 0 0 1 0 0 0 0 1 0 GCLK[1]
0 0 0 1 0 0 0 1 0 0 GCLK[2]
0 0 0 1 0 0 1 0 0 0 GCLK[3]
0 0 0 1 0 1 0 0 0 0 DBL_E1[4]
0 0 0 1 1 0 0 0 0 0 DBL_E0[4]
0 0 1 0 0 0 0 0 0 1 GCLK[4]
0 0 1 0 0 0 0 0 1 0 GCLK[5]
0 0 1 0 0 0 0 1 0 0 GCLK[6]
0 0 1 0 0 0 1 0 0 0 GCLK[7]
0 0 1 0 0 1 0 0 0 0 DBL_W1[4]
0 0 1 0 1 0 0 0 0 0 DBL_W2[4]
0 1 0 0 0 0 0 0 0 1 HEX_S3[4]
0 1 0 0 0 0 0 0 1 0 HEX_N3[4]
0 1 0 0 0 0 0 1 0 0 HEX_S2[4]
0 1 0 0 0 0 1 0 0 0 HEX_N4[4]
0 1 0 0 0 1 0 0 0 0 HEX_N5[4]
0 1 0 0 1 0 0 0 0 0 HEX_S1[4]
1 0 0 0 0 0 0 0 0 1 HEX_S6[4]
1 0 0 0 0 0 0 0 1 0 HEX_N0[4]
1 0 0 0 0 0 0 1 0 0 HEX_S5[4]
1 0 0 0 0 0 1 0 0 0 HEX_N1[4]
1 0 0 0 0 1 0 0 0 0 HEX_S4[4]
1 0 0 0 1 0 0 0 0 0 HEX_N2[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[0]
Bits Destination
MAIN[11][27] MAIN[11][29] MAIN[11][28] MAIN[11][26] MAIN[10][31] MAIN[10][26] MAIN[12][25] MAIN[12][31] IMUX_FAN_BX[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[1]
Bits Destination
MAIN[8][35] MAIN[8][36] MAIN[8][34] MAIN[9][32] MAIN[8][37] MAIN[9][33] MAIN[8][33] MAIN[10][35] IMUX_FAN_BX[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[2]
Bits Destination
MAIN[12][27] MAIN[12][29] MAIN[12][28] MAIN[11][30] MAIN[11][31] MAIN[10][29] MAIN[12][30] MAIN[12][26] IMUX_FAN_BX[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[3]
Bits Destination
MAIN[9][35] MAIN[9][36] MAIN[9][34] MAIN[10][33] MAIN[8][32] MAIN[9][37] MAIN[8][38] MAIN[10][36] IMUX_FAN_BX[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[0]
Bits Destination
MAIN[9][27] MAIN[9][29] MAIN[9][28] MAIN[8][31] MAIN[8][25] MAIN[9][26] MAIN[10][30] MAIN[10][27] IMUX_FAN_BY[0]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[1]
Bits Destination
MAIN[12][35] MAIN[12][34] MAIN[12][36] MAIN[11][33] MAIN[12][37] MAIN[11][32] MAIN[12][33] MAIN[10][34] IMUX_FAN_BY[1]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[2]
Bits Destination
MAIN[8][27] MAIN[8][29] MAIN[8][28] MAIN[8][26] MAIN[8][30] MAIN[9][30] MAIN[9][31] MAIN[10][28] IMUX_FAN_BY[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[3]
Bits Destination
MAIN[11][35] MAIN[11][34] MAIN[11][36] MAIN[11][37] MAIN[12][32] MAIN[10][32] MAIN[12][38] MAIN[10][37] IMUX_FAN_BY[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[2]
Bits Destination
MAIN[9][54] MAIN[9][53] MAIN[9][55] MAIN[9][57] MAIN[8][57] MAIN[9][52] MAIN[8][56] MAIN[10][51] IMUX_DATA[2]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[3]
Bits Destination
MAIN[12][20] MAIN[12][22] MAIN[12][21] MAIN[11][20] MAIN[11][25] MAIN[10][23] MAIN[12][19] MAIN[12][23] IMUX_DATA[3]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[16]
Bits Destination
MAIN[8][42] MAIN[8][43] MAIN[8][41] MAIN[9][38] MAIN[8][40] MAIN[9][43] MAIN[8][44] MAIN[10][41] IMUX_DATA[16]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[17]
Bits Destination
MAIN[11][10] MAIN[11][8] MAIN[11][9] MAIN[11][11] MAIN[11][6] MAIN[10][13] MAIN[12][7] MAIN[12][6] IMUX_DATA[17]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[18]
Bits Destination
MAIN[8][54] MAIN[8][53] MAIN[8][55] MAIN[9][51] MAIN[8][52] MAIN[9][56] MAIN[10][55] MAIN[10][53] IMUX_DATA[18]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[19]
Bits Destination
MAIN[11][23] MAIN[11][22] MAIN[11][21] MAIN[11][24] MAIN[10][21] MAIN[10][25] MAIN[12][24] MAIN[12][18] IMUX_DATA[19]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[20]
Bits Destination
MAIN[9][1] MAIN[9][2] MAIN[9][3] MAIN[8][0] MAIN[8][5] MAIN[9][5] MAIN[10][1] MAIN[10][4] IMUX_DATA[20]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[21]
Bits Destination
MAIN[12][48] MAIN[12][47] MAIN[12][49] MAIN[11][49] MAIN[12][46] MAIN[11][44] MAIN[10][49] MAIN[10][46] IMUX_DATA[21]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[22]
Bits Destination
MAIN[9][17] MAIN[9][16] MAIN[9][15] MAIN[8][12] MAIN[8][13] MAIN[9][18] MAIN[9][13] MAIN[10][18] IMUX_DATA[22]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[23]
Bits Destination
MAIN[12][60] MAIN[12][61] MAIN[12][62] MAIN[11][63] MAIN[12][59] MAIN[10][56] MAIN[10][60] MAIN[11][59] IMUX_DATA[23]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[24]
Bits Destination
MAIN[12][42] MAIN[12][41] MAIN[12][43] MAIN[11][43] MAIN[12][40] MAIN[11][38] MAIN[12][44] MAIN[10][40] IMUX_DATA[24]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[25]
Bits Destination
MAIN[9][10] MAIN[9][8] MAIN[9][9] MAIN[8][6] MAIN[8][7] MAIN[9][11] MAIN[9][6] MAIN[10][12] IMUX_DATA[25]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[26]
Bits Destination
MAIN[12][54] MAIN[12][55] MAIN[12][53] MAIN[11][56] MAIN[12][52] MAIN[11][51] MAIN[10][54] MAIN[10][52] IMUX_DATA[26]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[9]
0 0 0 0 0 0 1 0 OMUX_S3
0 0 0 0 0 1 0 0 IMUX_FAN_BX[1]
0 0 0 0 1 0 0 0 DBL_N2[4]
0 0 1 0 0 0 0 1 DBL_S1[4]
0 0 1 0 0 0 1 0 OMUX_WS1
0 0 1 0 0 1 0 0 DBL_E1[5]
0 0 1 0 1 0 0 0 OMUX_N11
0 0 1 1 0 0 0 0 IMUX_FAN_BX[0]
0 1 1 0 0 0 0 1 OMUX_SE3
0 1 1 0 0 0 1 0 OMUX_W9
0 1 1 0 0 1 0 0 DBL_S2[4]
0 1 1 0 1 0 0 0 DBL_W2[5]
0 1 1 1 0 0 0 0 DBL_W1[4]
1 0 0 0 0 0 0 1 DBL_S2[5]
1 0 0 0 0 0 1 0 DBL_W1[5]
1 0 0 0 0 1 0 0 OMUX_E8
1 0 0 0 1 0 0 0 DBL_W0[4]
1 0 0 1 0 0 0 0 DBL_E2[5]
1 1 0 0 0 0 0 1 DBL_N1[4]
1 1 0 0 0 0 1 0 DBL_W2[4]
1 1 0 0 0 1 0 0 DBL_E1[4]
1 1 0 0 1 0 0 0 DBL_E2[4]
1 1 0 1 0 0 0 0 DBL_E0[5]
1 1 1 0 0 0 0 1 DBL_N1[5]
1 1 1 0 0 0 1 0 DBL_N2[5]
1 1 1 0 0 1 0 0 DBL_S0[4]
1 1 1 1 0 0 0 0 DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[27]
Bits Destination
MAIN[9][23] MAIN[9][22] MAIN[9][21] MAIN[8][18] MAIN[8][24] MAIN[9][24] MAIN[10][20] MAIN[10][24] IMUX_DATA[27]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_N1[3]
0 0 0 0 0 0 1 0 DBL_N2[3]
0 0 0 0 0 1 0 0 DBL_S2[3]
0 0 0 0 1 0 0 0 DBL_S0[2]
0 0 0 1 0 0 0 0 DBL_S1[2]
0 0 1 0 0 0 0 1 OMUX_S4
0 0 1 0 0 0 1 0 OMUX_W6
0 0 1 0 0 1 0 0 IMUX_FAN_BX[3]
0 0 1 0 1 0 0 0 OMUX_N12
0 0 1 1 0 0 0 0 DBL_W0[2]
0 1 1 0 0 0 0 1 DBL_S2[2]
0 1 1 0 0 0 1 0 DBL_E1[3]
0 1 1 0 0 1 0 0 DBL_W2[3]
0 1 1 0 1 0 0 0 DBL_W1[2]
0 1 1 1 0 0 0 0 IMUX_FAN_BX[2]
1 0 0 0 0 0 0 1 DBL_N1[2]
1 0 0 0 0 0 1 0 DBL_W2[2]
1 0 0 0 0 1 0 0 DBL_E2[2]
1 0 0 0 1 0 0 0 DBL_E1[2]
1 0 0 1 0 0 0 0 DBL_S1[3]
1 1 0 0 0 0 0 1 DBL_N2[2]
1 1 0 0 0 0 1 0 DBL_W1[3]
1 1 0 0 0 1 0 0 OMUX_E7
1 1 0 0 1 0 0 0 DBL_E0[3]
1 1 0 1 0 0 0 0 DBL_E2[3]
1 1 1 0 0 0 0 1 OMUX[6]
1 1 1 0 0 0 1 0 OMUX_WN14
1 1 1 0 0 1 0 0 OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[28]
Bits Destination
MAIN[11][1] MAIN[11][2] MAIN[11][3] MAIN[11][5] MAIN[10][0] MAIN[10][5] MAIN[12][5] MAIN[12][0] IMUX_DATA[28]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[29]
Bits Destination
MAIN[8][48] MAIN[8][49] MAIN[8][47] MAIN[9][44] MAIN[8][46] MAIN[9][49] MAIN[10][48] MAIN[10][47] IMUX_DATA[29]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[30]
Bits Destination
MAIN[11][17] MAIN[11][16] MAIN[11][15] MAIN[11][18] MAIN[11][13] MAIN[10][19] MAIN[12][13] MAIN[12][12] IMUX_DATA[30]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 DBL_S1[1]
0 0 0 0 0 0 1 0 DBL_S0[0]
0 0 0 0 0 1 0 0 DBL_N1[1]
0 0 0 0 1 0 0 0 DBL_N2[1]
0 0 0 1 0 0 0 0 IMUX_FAN_BY[0]
0 0 1 0 0 0 0 1 DBL_E1[0]
0 0 1 0 0 0 1 0 OMUX_NW10
0 0 1 0 1 0 0 0 OMUX_EN8
0 0 1 1 0 0 0 0 DBL_W2[1]
0 1 1 0 0 0 0 1 OMUX[2]
0 1 1 0 0 0 1 0 DBL_E1[1]
0 1 1 0 0 1 0 0 DBL_S1[0]
0 1 1 0 1 0 0 0 DBL_S2[0]
0 1 1 1 0 0 0 0 DBL_S2[1]
1 0 0 0 0 0 0 1 DBL_E0[0]
1 0 0 0 0 0 1 0 OMUX_W1
1 0 0 0 0 1 0 0 DBL_N1[0]
1 0 0 0 1 0 0 0 DBL_W2[0]
1 0 0 1 0 0 0 0 DBL_E2[0]
1 1 0 0 0 0 0 1 DBL_E2[1]
1 1 0 0 0 0 1 0 DBL_W1[0]
1 1 0 0 0 1 0 0 DBL_N2[0]
1 1 0 0 1 0 0 0 DBL_W1[1]
1 1 0 1 0 0 0 0 DBL_W0[0]
1 1 1 0 0 0 0 1 IMUX_FAN_BY[1]
1 1 1 0 0 0 1 0 OMUX_S0
1 1 1 0 0 1 0 0 OMUX_E2
1 1 1 1 0 0 0 0 OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[31]
Bits Destination
MAIN[8][60] MAIN[8][62] MAIN[8][61] MAIN[10][57] MAIN[8][59] MAIN[9][63] MAIN[10][61] MAIN[9][59] IMUX_DATA[31]
Source
0 0 0 0 0 0 0 0 off
0 0 0 0 0 0 0 1 OMUX[13]
0 0 0 0 0 0 1 0 OMUX_SW5
0 0 0 0 1 0 0 0 IMUX_FAN_BY[2]
0 1 0 0 0 0 0 1 DBL_S2[6]
0 1 0 0 0 0 1 0 DBL_E1[7]
0 1 0 0 0 1 0 0 DBL_W2[7]
0 1 0 0 1 0 0 0 DBL_E0[7]
0 1 0 1 0 0 0 0 DBL_S1[6]
0 1 1 0 0 0 0 1 OMUX_N15
0 1 1 0 0 0 1 0 OMUX_S5
0 1 1 0 0 1 0 0 OMUX_ES7
0 1 1 0 1 0 0 0 OMUX_E13
0 1 1 1 0 0 0 0 OMUX_W14
1 0 0 0 0 0 0 1 DBL_N2[6]
1 0 0 0 0 0 1 0 DBL_W1[7]
1 0 0 0 0 1 0 0 DBL_E2[7]
1 0 0 0 1 0 0 0 DBL_W0[6]
1 0 0 1 0 0 0 0 DBL_W1[6]
1 0 1 0 0 0 0 1 DBL_N1[6]
1 0 1 0 0 0 1 0 DBL_W2[6]
1 0 1 0 0 1 0 0 DBL_S1[7]
1 0 1 0 1 0 0 0 DBL_E2[6]
1 0 1 1 0 0 0 0 DBL_E1[6]
1 1 1 0 0 0 0 1 DBL_N1[7]
1 1 1 0 0 0 1 0 DBL_N2[7]
1 1 1 0 0 1 0 0 DBL_S2[7]
1 1 1 0 1 0 0 0 IMUX_FAN_BY[3]
1 1 1 1 0 0 0 0 DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[12]
Bits Destination
MAIN[3][23] MAIN[3][22] MAIN[3][21] OUT_SEC[12]
Source
0 0 0 off
0 0 1 IMUX_DATA[31]
0 1 0 IMUX_DATA[23]
0 1 1 IMUX_CLK_OPTINV[3]
1 0 0 IMUX_DATA[19]
1 0 1 IMUX_DATA[3]
1 1 0 IMUX_DATA[27]
spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[13]
Bits Destination
MAIN[3][16] MAIN[3][18] MAIN[3][17] OUT_SEC[13]
Source
0 0 0 off
0 0 1 IMUX_DATA[22]
0 1 0 IMUX_DATA[30]
0 1 1 IMUX_CLK_OPTINV[2]
1 0 0 IMUX_DATA[18]
1 0 1 IMUX_DATA[26]
spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[14]
Bits Destination
MAIN[3][48] MAIN[3][49] MAIN[3][50] OUT_SEC[14]
Source
0 0 0 off
0 0 1 IMUX_DATA[29]
0 1 0 IMUX_DATA[21]
0 1 1 IMUX_CLK_OPTINV[1]
1 0 0 IMUX_DATA[17]
1 0 1 IMUX_DATA[2]
1 1 0 IMUX_DATA[25]
spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[15]
Bits Destination
MAIN[3][42] MAIN[3][41] MAIN[3][40] OUT_SEC[15]
Source
0 0 0 off
0 0 1 IMUX_DATA[16]
0 1 0 IMUX_DATA[20]
0 1 1 IMUX_DATA[24]
1 0 0 IMUX_DATA[28]