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Interconnect tiles

The interconnect tiles are 19×64 bits. The space on the left is unused by the interconnect tile, and contains data for whatever primitive is associated with the interconnect tile.

INT_CLB

Used with CLB tiles and the corner tiles.

Tile INT_CLB

Cells: 1

Switchbox INT

spartan3 INT_CLB switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[5][26]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[5][63]
spartan3 INT_CLB switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][6]MAIN[6][7]MAIN[7][0]MAIN[7][7]MAIN[6][3]MAIN[7][4]MAIN[6][2]MAIN[6][5]OMUX[0]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][1]MAIN[6][0]MAIN[7][1]MAIN[7][6]MAIN[6][4]MAIN[7][3]MAIN[7][2]MAIN[7][5]OMUX[1]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][9]MAIN[6][8]MAIN[7][15]MAIN[7][8]MAIN[6][12]MAIN[7][11]MAIN[6][13]MAIN[6][10]OMUX[2]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][14]MAIN[6][15]MAIN[7][14]MAIN[7][9]MAIN[6][11]MAIN[7][12]MAIN[7][13]MAIN[7][10]OMUX[3]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][22]MAIN[6][23]MAIN[7][16]MAIN[7][23]MAIN[6][19]MAIN[7][20]MAIN[6][18]MAIN[6][21]OMUX[4]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][17]MAIN[6][16]MAIN[7][17]MAIN[7][22]MAIN[6][20]MAIN[7][19]MAIN[7][18]MAIN[7][21]OMUX[5]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][25]MAIN[6][24]MAIN[7][31]MAIN[7][24]MAIN[6][28]MAIN[7][27]MAIN[6][29]MAIN[6][26]OMUX[6]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][30]MAIN[6][31]MAIN[7][30]MAIN[7][25]MAIN[6][27]MAIN[7][28]MAIN[7][29]MAIN[7][26]OMUX[7]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][38]MAIN[6][39]MAIN[7][32]MAIN[7][39]MAIN[6][35]MAIN[7][36]MAIN[6][34]MAIN[6][37]OMUX[8]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][33]MAIN[6][32]MAIN[7][33]MAIN[7][38]MAIN[6][36]MAIN[7][35]MAIN[7][34]MAIN[7][37]OMUX[9]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][41]MAIN[6][40]MAIN[7][47]MAIN[7][40]MAIN[6][44]MAIN[7][43]MAIN[6][45]MAIN[6][42]OMUX[10]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][46]MAIN[6][47]MAIN[7][46]MAIN[7][41]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[7][42]OMUX[11]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][54]MAIN[6][55]MAIN[7][48]MAIN[7][55]MAIN[6][51]MAIN[7][52]MAIN[6][50]MAIN[6][53]OMUX[12]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][49]MAIN[6][48]MAIN[7][49]MAIN[7][54]MAIN[6][52]MAIN[7][51]MAIN[7][50]MAIN[7][53]OMUX[13]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][57]MAIN[6][56]MAIN[7][63]MAIN[7][56]MAIN[6][60]MAIN[7][59]MAIN[6][61]MAIN[6][58]OMUX[14]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][62]MAIN[6][63]MAIN[7][62]MAIN[7][57]MAIN[6][59]MAIN[7][60]MAIN[7][61]MAIN[7][58]OMUX[15]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_CLB switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_CLB switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_CLB switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_CLB switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_CLB switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_CLB switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_CLB switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_CLB switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_CLB switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_CLB switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_CLB switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_CLB switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_CLB switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_CLB switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_CLB switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_CLB switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_CLB switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_CLB switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_CLB switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_CLB switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_CLB switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_CLB switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_CLB switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_CLB switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_CLB switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_CLB switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_CLB switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_CLB switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_CLB switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_CLB switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_CLB switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_CLB switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_CLB switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_CLB switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_CLB switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_CLB switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_CLB switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_CLB switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_CLB switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_CLB switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_CLB switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_CLB switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_CLB switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_CLB switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_CLB switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_CLB switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][24]MAIN[5][25]MAIN[4][24]MAIN[4][26]MAIN[4][21]MAIN[4][23]MAIN[5][23]MAIN[4][20]MAIN[4][16]MAIN[5][19]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][62]MAIN[4][63]MAIN[5][60]MAIN[4][60]MAIN[5][62]MAIN[5][59]IMUX_CE[3]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_CLB rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - INT: mux IMUX_CE[3] bit 4 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - INT: mux IMUX_CE[3] bit 2 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[14] bit 3 INT: mux OMUX[15] bit 2 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 INT: mux IMUX_CE[3] bit 0 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 2 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 7 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 4 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 4 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 7 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 3 INT: mux OMUX[13] bit 2 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 7 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 4 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 4 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[8] bit 7 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 6 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 3 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - - - INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 5 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - - INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 5 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 3 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_CLK[0] bit 6 INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[6] bit 7 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_CLK[0] bit 7 INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 4 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[0] bit 3 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 4 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[4] bit 7 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_CLK[0] bit 5 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_CLK[0] bit 2 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 2 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[4] bit 3 INT: mux OMUX[5] bit 2 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_CLK[0] bit 1 INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 3 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 2 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 7 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 4 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 4 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 7 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 2 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 3 INT: mux OMUX[1] bit 2 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_CLB_FC

Used with CLB tiles and the corner tiles — FPGAcore variant.

Tile INT_CLB_FC

Cells: 1

Switchbox INT

spartan3 INT_CLB_FC switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[5][26]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[5][63]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][6]MAIN[6][7]MAIN[7][0]MAIN[7][7]MAIN[6][3]MAIN[7][4]MAIN[6][2]MAIN[6][5]OMUX[0]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][1]MAIN[6][0]MAIN[7][1]MAIN[7][6]MAIN[6][4]MAIN[7][3]MAIN[7][2]MAIN[7][5]OMUX[1]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][9]MAIN[6][8]MAIN[7][15]MAIN[7][8]MAIN[6][12]MAIN[7][11]MAIN[6][13]MAIN[6][10]OMUX[2]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][14]MAIN[6][15]MAIN[7][14]MAIN[7][9]MAIN[6][11]MAIN[7][12]MAIN[7][13]MAIN[7][10]OMUX[3]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][22]MAIN[6][23]MAIN[7][16]MAIN[7][23]MAIN[6][19]MAIN[7][20]MAIN[6][18]MAIN[6][21]OMUX[4]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][17]MAIN[6][16]MAIN[7][17]MAIN[7][22]MAIN[6][20]MAIN[7][19]MAIN[7][18]MAIN[7][21]OMUX[5]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][25]MAIN[6][24]MAIN[7][31]MAIN[7][24]MAIN[6][28]MAIN[7][27]MAIN[6][29]MAIN[6][26]OMUX[6]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][30]MAIN[6][31]MAIN[7][30]MAIN[7][25]MAIN[6][27]MAIN[7][28]MAIN[7][29]MAIN[7][26]OMUX[7]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][38]MAIN[6][39]MAIN[7][32]MAIN[7][39]MAIN[6][35]MAIN[7][36]MAIN[6][34]MAIN[6][37]OMUX[8]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][33]MAIN[6][32]MAIN[7][33]MAIN[7][38]MAIN[6][36]MAIN[7][35]MAIN[7][34]MAIN[7][37]OMUX[9]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][41]MAIN[6][40]MAIN[7][47]MAIN[7][40]MAIN[6][44]MAIN[7][43]MAIN[6][45]MAIN[6][42]OMUX[10]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][46]MAIN[6][47]MAIN[7][46]MAIN[7][41]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[7][42]OMUX[11]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][54]MAIN[6][55]MAIN[7][48]MAIN[7][55]MAIN[6][51]MAIN[7][52]MAIN[6][50]MAIN[6][53]OMUX[12]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][49]MAIN[6][48]MAIN[7][49]MAIN[7][54]MAIN[6][52]MAIN[7][51]MAIN[7][50]MAIN[7][53]OMUX[13]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][57]MAIN[6][56]MAIN[7][63]MAIN[7][56]MAIN[6][60]MAIN[7][59]MAIN[6][61]MAIN[6][58]OMUX[14]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][62]MAIN[6][63]MAIN[7][62]MAIN[7][57]MAIN[6][59]MAIN[7][60]MAIN[7][61]MAIN[7][58]OMUX[15]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_CLB_FC switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11100HEX_S7[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11100HEX_S3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
spartan3 INT_CLB_FC switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_CLB_FC switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_CLB_FC switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_CLB_FC switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_CLB_FC switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][24]MAIN[5][25]MAIN[4][24]MAIN[4][26]MAIN[4][21]MAIN[4][23]MAIN[5][23]MAIN[4][20]MAIN[4][16]MAIN[5][19]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][62]MAIN[4][63]MAIN[5][60]MAIN[4][60]MAIN[5][62]MAIN[5][59]IMUX_CE[3]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_CLB_FC switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_CLB_FC rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - INT: mux IMUX_CE[3] bit 4 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - INT: mux IMUX_CE[3] bit 2 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[14] bit 3 INT: mux OMUX[15] bit 2 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 INT: mux IMUX_CE[3] bit 0 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 2 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 7 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 4 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 4 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 7 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 -
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 3 INT: mux OMUX[13] bit 2 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 -
B48 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 -
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 -
B46 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 -
B45 - - - - INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 7 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 4 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 4 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 -
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[8] bit 7 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 6 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 3 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 -
B32 - - - - - - INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 5 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 -
B31 - - - - - - INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 5 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 -
B30 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 -
B29 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 3 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_CLK[0] bit 6 INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[6] bit 7 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_CLK[0] bit 7 INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 4 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 -
B23 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[0] bit 3 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 4 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[4] bit 7 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_CLK[0] bit 5 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_CLK[0] bit 2 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 2 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[4] bit 3 INT: mux OMUX[5] bit 2 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 -
B16 - - - - INT: mux IMUX_CLK[0] bit 1 INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 -
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 -
B14 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 -
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 3 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 2 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 7 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 -
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 4 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 4 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 7 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 2 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 3 INT: mux OMUX[1] bit 2 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_IOI_S3

Used with IOI tiles on Spartan 3.

Tile INT_IOI_S3

Cells: 1

Switchbox INT

spartan3 INT_IOI_S3 switchbox INT programmable inverters
DestinationSourceBit
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][6]MAIN[6][7]MAIN[6][3]MAIN[7][0]MAIN[7][7]MAIN[7][4]MAIN[6][2]MAIN[6][5]OMUX[0]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][1]MAIN[6][0]MAIN[6][4]MAIN[7][1]MAIN[7][6]MAIN[7][3]MAIN[7][2]MAIN[7][5]OMUX[1]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][9]MAIN[6][8]MAIN[6][12]MAIN[7][15]MAIN[7][8]MAIN[7][11]MAIN[6][13]MAIN[6][10]OMUX[2]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][14]MAIN[6][15]MAIN[6][11]MAIN[7][14]MAIN[7][9]MAIN[7][12]MAIN[7][13]MAIN[7][10]OMUX[3]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][22]MAIN[6][23]MAIN[6][19]MAIN[7][16]MAIN[7][23]MAIN[7][20]MAIN[6][18]MAIN[6][21]OMUX[4]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][17]MAIN[6][16]MAIN[6][20]MAIN[7][17]MAIN[7][22]MAIN[7][19]MAIN[7][18]MAIN[7][21]OMUX[5]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][25]MAIN[6][24]MAIN[6][28]MAIN[7][31]MAIN[7][24]MAIN[7][27]MAIN[6][29]MAIN[6][26]OMUX[6]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][30]MAIN[6][31]MAIN[6][27]MAIN[7][30]MAIN[7][25]MAIN[7][28]MAIN[7][29]MAIN[7][26]OMUX[7]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][38]MAIN[6][39]MAIN[6][35]MAIN[7][32]MAIN[7][39]MAIN[7][36]MAIN[6][34]MAIN[6][37]OMUX[8]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][33]MAIN[6][32]MAIN[6][36]MAIN[7][33]MAIN[7][38]MAIN[7][35]MAIN[7][34]MAIN[7][37]OMUX[9]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][41]MAIN[6][40]MAIN[6][44]MAIN[7][47]MAIN[7][40]MAIN[7][43]MAIN[6][45]MAIN[6][42]OMUX[10]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][46]MAIN[6][47]MAIN[6][43]MAIN[7][46]MAIN[7][41]MAIN[7][44]MAIN[7][45]MAIN[7][42]OMUX[11]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][54]MAIN[6][55]MAIN[6][51]MAIN[7][48]MAIN[7][55]MAIN[7][52]MAIN[6][50]MAIN[6][53]OMUX[12]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][49]MAIN[6][48]MAIN[6][52]MAIN[7][49]MAIN[7][54]MAIN[7][51]MAIN[7][50]MAIN[7][53]OMUX[13]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][57]MAIN[6][56]MAIN[6][60]MAIN[7][63]MAIN[7][56]MAIN[7][59]MAIN[6][61]MAIN[6][58]OMUX[14]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][62]MAIN[6][63]MAIN[6][59]MAIN[7][62]MAIN[7][57]MAIN[7][60]MAIN[7][61]MAIN[7][58]OMUX[15]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3 switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3 switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_IOI_S3 switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3 switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3 switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3 switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3 switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3 switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3 switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3 switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[0]
BitsDestination
MAIN[4][23]MAIN[4][22]MAIN[5][23]MAIN[5][16]MAIN[4][18]MAIN[5][20]MAIN[4][19]MAIN[4][21]IMUX_IOCLK[0]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[1]
BitsDestination
MAIN[4][16]MAIN[4][17]MAIN[5][22]MAIN[5][17]MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][21]IMUX_IOCLK[1]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[2]
BitsDestination
MAIN[4][24]MAIN[4][25]MAIN[5][24]MAIN[5][31]MAIN[4][29]MAIN[5][27]MAIN[4][28]MAIN[4][26]IMUX_IOCLK[2]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[3]
BitsDestination
MAIN[4][31]MAIN[4][30]MAIN[5][25]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[4][27]MAIN[5][26]IMUX_IOCLK[3]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[4]
BitsDestination
MAIN[4][39]MAIN[4][38]MAIN[5][39]MAIN[5][32]MAIN[4][34]MAIN[5][36]MAIN[4][35]MAIN[4][37]IMUX_IOCLK[4]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[5]
BitsDestination
MAIN[4][32]MAIN[4][33]MAIN[5][38]MAIN[5][33]MAIN[5][34]MAIN[5][35]MAIN[4][36]MAIN[5][37]IMUX_IOCLK[5]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[6]
BitsDestination
MAIN[4][40]MAIN[4][41]MAIN[5][40]MAIN[5][47]MAIN[4][45]MAIN[5][43]MAIN[4][44]MAIN[4][42]IMUX_IOCLK[6]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_IOCLK[7]
BitsDestination
MAIN[4][47]MAIN[4][46]MAIN[5][41]MAIN[5][46]MAIN[5][45]MAIN[5][44]MAIN[4][43]MAIN[5][42]IMUX_IOCLK[7]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3 switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10

Bitstream

spartan3 INT_IOI_S3 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 4 - - - - - INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - - - INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 4 - - - - - INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 - - - - - INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - INT: mux OMUX[14] bit 5 INT: mux OMUX[15] bit 2 - - - - - INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 - INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 2 - - - - - INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 - - - - - INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 7 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 - INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 - INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 7 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 5 INT: mux OMUX[13] bit 2 - INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 - - INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 4 INT: mux IMUX_DATA[29] bit 7 - INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_IOCLK[7] bit 7 INT: mux IMUX_IOCLK[6] bit 4 INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 4 INT: mux IMUX_DATA[29] bit 5 - INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_IOCLK[7] bit 6 INT: mux IMUX_IOCLK[7] bit 4 INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[29] bit 3 - INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_IOCLK[6] bit 3 INT: mux IMUX_IOCLK[7] bit 3 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 - - INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_IOCLK[6] bit 1 INT: mux IMUX_IOCLK[7] bit 2 INT: mux OMUX[10] bit 5 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_IOCLK[7] bit 1 INT: mux IMUX_IOCLK[6] bit 2 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_IOCLK[6] bit 0 INT: mux IMUX_IOCLK[7] bit 0 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_IOCLK[6] bit 6 INT: mux IMUX_IOCLK[7] bit 5 INT: mux OMUX[10] bit 7 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_IOCLK[6] bit 7 INT: mux IMUX_IOCLK[6] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_IOCLK[4] bit 7 INT: mux IMUX_IOCLK[4] bit 5 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 3 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_IOCLK[4] bit 6 INT: mux IMUX_IOCLK[5] bit 5 INT: mux OMUX[8] bit 7 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_IOCLK[4] bit 0 INT: mux IMUX_IOCLK[5] bit 0 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - INT: mux IMUX_IOCLK[5] bit 1 INT: mux IMUX_IOCLK[4] bit 2 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - INT: mux IMUX_IOCLK[4] bit 1 INT: mux IMUX_IOCLK[5] bit 2 INT: mux OMUX[8] bit 5 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - INT: mux IMUX_IOCLK[4] bit 3 INT: mux IMUX_IOCLK[5] bit 3 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - INT: mux IMUX_IOCLK[5] bit 6 INT: mux IMUX_IOCLK[5] bit 4 INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - INT: mux IMUX_IOCLK[5] bit 7 INT: mux IMUX_IOCLK[4] bit 4 INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 4 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - INT: mux IMUX_IOCLK[3] bit 7 INT: mux IMUX_IOCLK[2] bit 4 INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 4 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - INT: mux IMUX_IOCLK[3] bit 6 INT: mux IMUX_IOCLK[3] bit 4 INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - INT: mux IMUX_IOCLK[2] bit 3 INT: mux IMUX_IOCLK[3] bit 3 INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - INT: mux IMUX_IOCLK[2] bit 1 INT: mux IMUX_IOCLK[3] bit 2 INT: mux OMUX[6] bit 5 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - INT: mux IMUX_IOCLK[3] bit 1 INT: mux IMUX_IOCLK[2] bit 2 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_IOCLK[2] bit 0 INT: mux IMUX_IOCLK[3] bit 0 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_IOCLK[2] bit 6 INT: mux IMUX_IOCLK[3] bit 5 INT: mux OMUX[6] bit 7 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[0] bit 3 - - - INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_IOCLK[2] bit 7 INT: mux IMUX_IOCLK[2] bit 5 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 3 - - - - - INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_IOCLK[0] bit 7 INT: mux IMUX_IOCLK[0] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 3 - - - - - INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_IOCLK[0] bit 6 INT: mux IMUX_IOCLK[1] bit 5 INT: mux OMUX[4] bit 7 INT: mux OMUX[5] bit 3 - - - - - INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_IOCLK[0] bit 0 INT: mux IMUX_IOCLK[1] bit 0 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 - - - - - INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_IOCLK[1] bit 1 INT: mux IMUX_IOCLK[0] bit 2 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 2 - - - - - INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_IOCLK[0] bit 1 INT: mux IMUX_IOCLK[1] bit 2 INT: mux OMUX[4] bit 5 INT: mux OMUX[5] bit 2 - INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 - - INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_IOCLK[0] bit 3 INT: mux IMUX_IOCLK[1] bit 3 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 - INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 - INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_IOCLK[1] bit 6 INT: mux IMUX_IOCLK[1] bit 4 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 - INT: mux IMUX_DATA[30] bit 7 - INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_IOCLK[1] bit 7 INT: mux IMUX_IOCLK[0] bit 4 INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 4 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 - INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 4 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 - INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 - - - INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - - - INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - - INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 5 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 - INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 2 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - - - INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 7 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 - INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 - INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 7 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 2 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 - - INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 - INT: mux IMUX_DATA[28] bit 5 - INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 - INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 - INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 4 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 - INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_IOI_FC

Used with IOI tiles on FPGAcore.

Tile INT_IOI_FC

Cells: 1

Switchbox INT

spartan3 INT_IOI_FC switchbox INT programmable inverters
DestinationSourceBit
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[5][63]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][7]MAIN[6][6]MAIN[6][2]MAIN[6][3]MAIN[7][0]MAIN[7][7]MAIN[6][5]OMUX[0]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][0]MAIN[6][1]MAIN[7][2]MAIN[6][4]MAIN[7][1]MAIN[7][6]MAIN[7][5]OMUX[1]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][8]MAIN[6][9]MAIN[6][13]MAIN[6][12]MAIN[7][15]MAIN[7][8]MAIN[6][10]OMUX[2]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][15]MAIN[6][14]MAIN[7][13]MAIN[6][11]MAIN[7][14]MAIN[7][9]MAIN[7][10]OMUX[3]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][23]MAIN[6][22]MAIN[6][18]MAIN[6][19]MAIN[7][16]MAIN[7][23]MAIN[6][21]OMUX[4]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][16]MAIN[6][17]MAIN[7][18]MAIN[6][20]MAIN[7][17]MAIN[7][22]MAIN[7][21]OMUX[5]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][24]MAIN[6][25]MAIN[6][29]MAIN[6][28]MAIN[7][31]MAIN[7][24]MAIN[6][26]OMUX[6]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][31]MAIN[6][30]MAIN[7][29]MAIN[6][27]MAIN[7][30]MAIN[7][25]MAIN[7][26]OMUX[7]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][39]MAIN[6][38]MAIN[6][34]MAIN[6][35]MAIN[7][32]MAIN[7][39]MAIN[6][37]OMUX[8]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][32]MAIN[6][33]MAIN[7][34]MAIN[6][36]MAIN[7][33]MAIN[7][38]MAIN[7][37]OMUX[9]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][40]MAIN[6][41]MAIN[6][45]MAIN[6][44]MAIN[7][47]MAIN[7][40]MAIN[6][42]OMUX[10]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][47]MAIN[6][46]MAIN[7][45]MAIN[6][43]MAIN[7][46]MAIN[7][41]MAIN[7][42]OMUX[11]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][55]MAIN[6][54]MAIN[6][50]MAIN[6][51]MAIN[7][48]MAIN[7][55]MAIN[6][53]OMUX[12]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][48]MAIN[6][49]MAIN[7][50]MAIN[6][52]MAIN[7][49]MAIN[7][54]MAIN[7][53]OMUX[13]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][56]MAIN[6][57]MAIN[6][61]MAIN[6][60]MAIN[7][63]MAIN[7][56]MAIN[6][58]OMUX[14]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][63]MAIN[6][62]MAIN[7][61]MAIN[6][59]MAIN[7][62]MAIN[7][57]MAIN[7][58]OMUX[15]
Source
0000000off
0000001OUT_FAN[4]
0000010OUT_FAN[5]
0000100OUT_SEC[8]
0100100OUT_FAN[6]
0110000OUT_SEC[10]
1100010OUT_SEC[11]
1100100OUT_FAN[7]
1101000OUT_SEC[9]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_FC switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_FC switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_FC switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_IOI_FC switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11100HEX_S7[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11100HEX_S3[6]
spartan3 INT_IOI_FC switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
spartan3 INT_IOI_FC switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
spartan3 INT_IOI_FC switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_IOI_FC switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_FC switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_FC switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_FC switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][62]MAIN[4][63]MAIN[5][60]MAIN[4][60]MAIN[5][62]MAIN[5][59]IMUX_CE[3]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[0]
BitsDestination
MAIN[4][23]MAIN[4][22]MAIN[5][23]MAIN[5][16]MAIN[4][18]MAIN[5][20]MAIN[4][19]MAIN[4][21]IMUX_IOCLK[0]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[1]
BitsDestination
MAIN[4][16]MAIN[4][17]MAIN[5][22]MAIN[5][17]MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][21]IMUX_IOCLK[1]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[2]
BitsDestination
MAIN[4][39]MAIN[4][38]MAIN[5][39]MAIN[5][32]MAIN[4][34]MAIN[5][36]MAIN[4][35]MAIN[4][37]IMUX_IOCLK[2]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[3]
BitsDestination
MAIN[4][32]MAIN[4][33]MAIN[5][38]MAIN[5][33]MAIN[5][34]MAIN[5][35]MAIN[4][36]MAIN[5][37]IMUX_IOCLK[3]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[4]
BitsDestination
MAIN[4][24]MAIN[4][25]MAIN[5][24]MAIN[5][31]MAIN[4][29]MAIN[5][27]MAIN[4][28]MAIN[4][26]IMUX_IOCLK[4]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[5]
BitsDestination
MAIN[4][31]MAIN[4][30]MAIN[5][25]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[4][27]MAIN[5][26]IMUX_IOCLK[5]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[6]
BitsDestination
MAIN[4][40]MAIN[4][41]MAIN[5][40]MAIN[5][47]MAIN[4][45]MAIN[5][43]MAIN[4][44]MAIN[4][42]IMUX_IOCLK[6]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_IOCLK[7]
BitsDestination
MAIN[4][47]MAIN[4][46]MAIN[5][41]MAIN[5][46]MAIN[5][45]MAIN[5][44]MAIN[4][43]MAIN[5][42]IMUX_IOCLK[7]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[25]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_IOI_FC switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[27]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_IOI_FC rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - INT: mux IMUX_CE[3] bit 4 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 2 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[7] bit 2 - INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[15] bit 5 INT: mux OMUX[15] bit 2 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 - INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[7] bit 6 - INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - INT: mux IMUX_CE[3] bit 2 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[14] bit 3 - INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[15] bit 7 - INT: mux IMUX_DATA[7] bit 7 - INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 INT: mux IMUX_CE[3] bit 0 INT: mux OMUX[15] bit 3 - INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[15] bit 0 - - INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 5 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 1 INT: mux IMUX_DATA[2] bit 1 - - INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 1 - INT: mux IMUX_DATA[2] bit 5 - INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 5 INT: mux OMUX[13] bit 1 - INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 -
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 - INT: mux IMUX_DATA[2] bit 6 - INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 3 - - INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 3 - INT: mux IMUX_DATA[13] bit 3 - INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 5 INT: mux OMUX[13] bit 2 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[25] bit 2 - - - INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 -
B48 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[5] bit 7 - INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 -
B47 - - - - INT: mux IMUX_IOCLK[7] bit 7 INT: mux IMUX_IOCLK[6] bit 4 INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[5] bit 6 - INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 -
B46 - - - - INT: mux IMUX_IOCLK[7] bit 6 INT: mux IMUX_IOCLK[7] bit 4 INT: mux OMUX[11] bit 5 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[13] bit 6 - INT: mux IMUX_DATA[5] bit 5 - INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 -
B45 - - - - INT: mux IMUX_IOCLK[6] bit 3 INT: mux IMUX_IOCLK[7] bit 3 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_IOCLK[6] bit 1 INT: mux IMUX_IOCLK[7] bit 2 INT: mux OMUX[10] bit 3 - - INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[5] bit 0 - INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_IOCLK[7] bit 1 INT: mux IMUX_IOCLK[6] bit 2 INT: mux OMUX[11] bit 3 - - - INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_IOCLK[6] bit 0 INT: mux IMUX_IOCLK[7] bit 0 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 - INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_IOCLK[6] bit 6 INT: mux IMUX_IOCLK[7] bit 5 INT: mux OMUX[10] bit 5 INT: mux OMUX[11] bit 1 - INT: mux IMUX_DATA[0] bit 5 - INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_IOCLK[6] bit 7 INT: mux IMUX_IOCLK[6] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 1 - INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_IOCLK[2] bit 7 INT: mux IMUX_IOCLK[2] bit 5 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 1 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 -
B38 - - - - INT: mux IMUX_IOCLK[2] bit 6 INT: mux IMUX_IOCLK[3] bit 5 INT: mux OMUX[8] bit 5 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[3] bit 1 - INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_IOCLK[2] bit 0 INT: mux IMUX_IOCLK[3] bit 0 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - INT: mux IMUX_IOCLK[3] bit 1 INT: mux IMUX_IOCLK[2] bit 2 INT: mux OMUX[9] bit 3 - INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - INT: mux IMUX_IOCLK[2] bit 1 INT: mux IMUX_IOCLK[3] bit 2 INT: mux OMUX[8] bit 3 - INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - INT: mux IMUX_IOCLK[2] bit 3 INT: mux IMUX_IOCLK[3] bit 3 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - INT: mux IMUX_IOCLK[3] bit 6 INT: mux IMUX_IOCLK[3] bit 4 INT: mux OMUX[9] bit 5 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 -
B32 - - - - INT: mux IMUX_IOCLK[3] bit 7 INT: mux IMUX_IOCLK[2] bit 4 INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 -
B31 - - - - INT: mux IMUX_IOCLK[5] bit 7 INT: mux IMUX_IOCLK[4] bit 4 INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 -
B30 - - - - INT: mux IMUX_IOCLK[5] bit 6 INT: mux IMUX_IOCLK[5] bit 4 INT: mux OMUX[7] bit 5 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 -
B29 - - - - INT: mux IMUX_IOCLK[4] bit 3 INT: mux IMUX_IOCLK[5] bit 3 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - INT: mux IMUX_IOCLK[4] bit 1 INT: mux IMUX_IOCLK[5] bit 2 INT: mux OMUX[6] bit 3 - INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - INT: mux IMUX_IOCLK[5] bit 1 INT: mux IMUX_IOCLK[4] bit 2 INT: mux OMUX[7] bit 3 - INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_IOCLK[4] bit 0 INT: mux IMUX_IOCLK[5] bit 0 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_IOCLK[4] bit 6 INT: mux IMUX_IOCLK[5] bit 5 INT: mux OMUX[6] bit 5 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 - INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_IOCLK[4] bit 7 INT: mux IMUX_IOCLK[4] bit 5 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 1 - - - - - INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 -
B23 - - - - INT: mux IMUX_IOCLK[0] bit 7 INT: mux IMUX_IOCLK[0] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 1 INT: mux IMUX_DATA[11] bit 4 - INT: mux IMUX_DATA[3] bit 2 - INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_IOCLK[0] bit 6 INT: mux IMUX_IOCLK[1] bit 5 INT: mux OMUX[4] bit 5 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[11] bit 6 - INT: mux IMUX_DATA[11] bit 0 - INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_IOCLK[0] bit 0 INT: mux IMUX_IOCLK[1] bit 0 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[11] bit 5 - - - INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_IOCLK[1] bit 1 INT: mux IMUX_IOCLK[0] bit 2 INT: mux OMUX[5] bit 3 - INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 - INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_IOCLK[0] bit 1 INT: mux IMUX_IOCLK[1] bit 2 INT: mux OMUX[4] bit 3 - INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 - INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_IOCLK[0] bit 3 INT: mux IMUX_IOCLK[1] bit 3 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 - - - - - INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_IOCLK[1] bit 6 INT: mux IMUX_IOCLK[1] bit 4 INT: mux OMUX[5] bit 5 INT: mux OMUX[5] bit 2 INT: mux IMUX_DATA[6] bit 4 - INT: mux IMUX_DATA[14] bit 2 - INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 -
B16 - - - - INT: mux IMUX_IOCLK[1] bit 7 INT: mux IMUX_IOCLK[0] bit 4 INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 2 INT: mux IMUX_DATA[6] bit 6 - INT: mux IMUX_DATA[6] bit 0 - INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 -
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 2 INT: mux IMUX_DATA[6] bit 5 - INT: mux IMUX_DATA[6] bit 3 - INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 -
B14 - - - - - - INT: mux OMUX[3] bit 5 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 -
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 - - - - - INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 3 - - INT: mux IMUX_DATA[9] bit 1 - INT: mux IMUX_DATA[1] bit 3 - INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 3 - INT: mux IMUX_DATA[9] bit 4 - INT: mux IMUX_DATA[1] bit 2 - INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[9] bit 7 - INT: mux IMUX_DATA[9] bit 0 - INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 5 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[9] bit 5 - INT: mux IMUX_DATA[1] bit 1 - INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 -
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 1 INT: mux IMUX_DATA[9] bit 6 - INT: mux IMUX_DATA[9] bit 3 - INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 1 - INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 - INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 5 INT: mux OMUX[1] bit 1 - - INT: mux IMUX_DATA[4] bit 1 - - INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 - - - - - INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 3 - INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 - INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 3 - INT: mux IMUX_DATA[4] bit 5 - INT: mux IMUX_DATA[12] bit 1 - INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[4] bit 6 - INT: mux IMUX_DATA[4] bit 3 - INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 5 INT: mux OMUX[1] bit 2 INT: mux IMUX_DATA[4] bit 7 - - - INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 2 - INT: mux IMUX_DATA[4] bit 2 - INT: mux IMUX_DATA[12] bit 4 - INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_IOI_S3E

Used with IOI tiles on Spartan 3E.

Tile INT_IOI_S3E

Cells: 1

Switchbox INT

spartan3 INT_IOI_S3E switchbox INT programmable inverters
DestinationSourceBit
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][6]MAIN[6][7]MAIN[7][0]MAIN[7][7]MAIN[6][3]MAIN[7][4]MAIN[6][2]MAIN[6][5]OMUX[0]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][1]MAIN[6][0]MAIN[7][1]MAIN[7][6]MAIN[6][4]MAIN[7][3]MAIN[7][2]MAIN[7][5]OMUX[1]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][9]MAIN[6][8]MAIN[7][15]MAIN[7][8]MAIN[6][12]MAIN[7][11]MAIN[6][13]MAIN[6][10]OMUX[2]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][14]MAIN[6][15]MAIN[7][14]MAIN[7][9]MAIN[6][11]MAIN[7][12]MAIN[7][13]MAIN[7][10]OMUX[3]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][22]MAIN[6][23]MAIN[7][16]MAIN[7][23]MAIN[6][19]MAIN[7][20]MAIN[6][18]MAIN[6][21]OMUX[4]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][17]MAIN[6][16]MAIN[7][17]MAIN[7][22]MAIN[6][20]MAIN[7][19]MAIN[7][18]MAIN[7][21]OMUX[5]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][25]MAIN[6][24]MAIN[7][31]MAIN[7][24]MAIN[6][28]MAIN[7][27]MAIN[6][29]MAIN[6][26]OMUX[6]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][30]MAIN[6][31]MAIN[7][30]MAIN[7][25]MAIN[6][27]MAIN[7][28]MAIN[7][29]MAIN[7][26]OMUX[7]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][38]MAIN[6][39]MAIN[7][32]MAIN[7][39]MAIN[6][35]MAIN[7][36]MAIN[6][34]MAIN[6][37]OMUX[8]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][33]MAIN[6][32]MAIN[7][33]MAIN[7][38]MAIN[6][36]MAIN[7][35]MAIN[7][34]MAIN[7][37]OMUX[9]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][41]MAIN[6][40]MAIN[7][47]MAIN[7][40]MAIN[6][44]MAIN[7][43]MAIN[6][45]MAIN[6][42]OMUX[10]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][46]MAIN[6][47]MAIN[7][46]MAIN[7][41]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[7][42]OMUX[11]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][54]MAIN[6][55]MAIN[7][48]MAIN[7][55]MAIN[6][51]MAIN[7][52]MAIN[6][50]MAIN[6][53]OMUX[12]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][49]MAIN[6][48]MAIN[7][49]MAIN[7][54]MAIN[6][52]MAIN[7][51]MAIN[7][50]MAIN[7][53]OMUX[13]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][57]MAIN[6][56]MAIN[7][63]MAIN[7][56]MAIN[6][60]MAIN[7][59]MAIN[6][61]MAIN[6][58]OMUX[14]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][62]MAIN[6][63]MAIN[7][62]MAIN[7][57]MAIN[6][59]MAIN[7][60]MAIN[7][61]MAIN[7][58]OMUX[15]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01010000OUT_SEC[9]
10000010OUT_SEC[10]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3E switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3E switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_IOI_S3E switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3E switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3E switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3E switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3E switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3E switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3E switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3E switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[0]
BitsDestination
MAIN[4][23]MAIN[4][22]MAIN[5][23]MAIN[5][16]MAIN[4][18]MAIN[5][20]MAIN[4][19]MAIN[4][21]IMUX_IOCLK[0]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[1]
BitsDestination
MAIN[4][16]MAIN[4][17]MAIN[5][22]MAIN[5][17]MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][21]IMUX_IOCLK[1]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[2]
BitsDestination
MAIN[4][24]MAIN[4][25]MAIN[5][24]MAIN[5][31]MAIN[4][29]MAIN[5][27]MAIN[4][28]MAIN[4][26]IMUX_IOCLK[2]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[3]
BitsDestination
MAIN[4][31]MAIN[4][30]MAIN[5][25]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[4][27]MAIN[5][26]IMUX_IOCLK[3]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[4]
BitsDestination
MAIN[4][39]MAIN[4][38]MAIN[5][39]MAIN[5][32]MAIN[4][34]MAIN[5][36]MAIN[4][35]MAIN[4][37]IMUX_IOCLK[4]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[5]
BitsDestination
MAIN[4][32]MAIN[4][33]MAIN[5][38]MAIN[5][33]MAIN[5][34]MAIN[5][35]MAIN[4][36]MAIN[5][37]IMUX_IOCLK[5]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[6]
BitsDestination
MAIN[4][40]MAIN[4][41]MAIN[5][40]MAIN[5][47]MAIN[4][45]MAIN[5][43]MAIN[4][44]MAIN[4][42]IMUX_IOCLK[6]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_IOCLK[7]
BitsDestination
MAIN[4][47]MAIN[4][46]MAIN[5][41]MAIN[5][46]MAIN[5][45]MAIN[5][44]MAIN[4][43]MAIN[5][42]IMUX_IOCLK[7]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3E switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_IOI_S3E rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - - - INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - INT: mux OMUX[14] bit 3 INT: mux OMUX[15] bit 2 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 - INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 2 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 7 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 4 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 4 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 7 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 3 INT: mux OMUX[13] bit 2 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_IOCLK[7] bit 7 INT: mux IMUX_IOCLK[6] bit 4 INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_IOCLK[7] bit 6 INT: mux IMUX_IOCLK[7] bit 4 INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_IOCLK[6] bit 3 INT: mux IMUX_IOCLK[7] bit 3 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_IOCLK[6] bit 1 INT: mux IMUX_IOCLK[7] bit 2 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_IOCLK[7] bit 1 INT: mux IMUX_IOCLK[6] bit 2 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_IOCLK[6] bit 0 INT: mux IMUX_IOCLK[7] bit 0 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_IOCLK[6] bit 6 INT: mux IMUX_IOCLK[7] bit 5 INT: mux OMUX[10] bit 7 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_IOCLK[6] bit 7 INT: mux IMUX_IOCLK[6] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 4 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_IOCLK[4] bit 7 INT: mux IMUX_IOCLK[4] bit 5 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 4 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_IOCLK[4] bit 6 INT: mux IMUX_IOCLK[5] bit 5 INT: mux OMUX[8] bit 7 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_IOCLK[4] bit 0 INT: mux IMUX_IOCLK[5] bit 0 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - INT: mux IMUX_IOCLK[5] bit 1 INT: mux IMUX_IOCLK[4] bit 2 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - INT: mux IMUX_IOCLK[4] bit 1 INT: mux IMUX_IOCLK[5] bit 2 INT: mux OMUX[8] bit 3 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - INT: mux IMUX_IOCLK[4] bit 3 INT: mux IMUX_IOCLK[5] bit 3 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - INT: mux IMUX_IOCLK[5] bit 6 INT: mux IMUX_IOCLK[5] bit 4 INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - INT: mux IMUX_IOCLK[5] bit 7 INT: mux IMUX_IOCLK[4] bit 4 INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 5 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - INT: mux IMUX_IOCLK[3] bit 7 INT: mux IMUX_IOCLK[2] bit 4 INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 5 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - INT: mux IMUX_IOCLK[3] bit 6 INT: mux IMUX_IOCLK[3] bit 4 INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - INT: mux IMUX_IOCLK[2] bit 3 INT: mux IMUX_IOCLK[3] bit 3 INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - INT: mux IMUX_IOCLK[2] bit 1 INT: mux IMUX_IOCLK[3] bit 2 INT: mux OMUX[6] bit 3 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - INT: mux IMUX_IOCLK[3] bit 1 INT: mux IMUX_IOCLK[2] bit 2 INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_IOCLK[2] bit 0 INT: mux IMUX_IOCLK[3] bit 0 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_IOCLK[2] bit 6 INT: mux IMUX_IOCLK[3] bit 5 INT: mux OMUX[6] bit 7 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_IOCLK[2] bit 7 INT: mux IMUX_IOCLK[2] bit 5 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 4 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_IOCLK[0] bit 7 INT: mux IMUX_IOCLK[0] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 4 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_IOCLK[0] bit 6 INT: mux IMUX_IOCLK[1] bit 5 INT: mux OMUX[4] bit 7 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_IOCLK[0] bit 0 INT: mux IMUX_IOCLK[1] bit 0 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_IOCLK[1] bit 1 INT: mux IMUX_IOCLK[0] bit 2 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 2 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_IOCLK[0] bit 1 INT: mux IMUX_IOCLK[1] bit 2 INT: mux OMUX[4] bit 3 INT: mux OMUX[5] bit 2 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_IOCLK[0] bit 3 INT: mux IMUX_IOCLK[1] bit 3 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_IOCLK[1] bit 6 INT: mux IMUX_IOCLK[1] bit 4 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_IOCLK[1] bit 7 INT: mux IMUX_IOCLK[0] bit 4 INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - - - INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - - INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 3 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 - INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 2 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - - - INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 7 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 - INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 4 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 4 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 7 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 2 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 3 INT: mux OMUX[1] bit 2 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_IOI_S3A_WE

Used with IOI tiles on Spartan 3A / 3A DSP that are on the left or right edge of the device.

Tile INT_IOI_S3A_WE

Cells: 1

Switchbox INT

spartan3 INT_IOI_S3A_WE switchbox INT programmable inverters
DestinationSourceBit
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][6]MAIN[6][7]MAIN[7][4]MAIN[7][0]MAIN[7][7]MAIN[6][3]MAIN[6][2]MAIN[6][5]OMUX[0]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][1]MAIN[6][0]MAIN[7][3]MAIN[7][1]MAIN[7][6]MAIN[6][4]MAIN[7][2]MAIN[7][5]OMUX[1]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][9]MAIN[6][8]MAIN[7][11]MAIN[7][15]MAIN[7][8]MAIN[6][12]MAIN[6][13]MAIN[6][10]OMUX[2]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][14]MAIN[6][15]MAIN[7][12]MAIN[7][14]MAIN[7][9]MAIN[6][11]MAIN[7][13]MAIN[7][10]OMUX[3]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][22]MAIN[6][23]MAIN[7][20]MAIN[7][16]MAIN[7][23]MAIN[6][19]MAIN[6][18]MAIN[6][21]OMUX[4]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][17]MAIN[6][16]MAIN[7][19]MAIN[7][17]MAIN[7][22]MAIN[6][20]MAIN[7][18]MAIN[7][21]OMUX[5]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][25]MAIN[6][24]MAIN[7][27]MAIN[7][31]MAIN[7][24]MAIN[6][28]MAIN[6][29]MAIN[6][26]OMUX[6]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][30]MAIN[6][31]MAIN[7][28]MAIN[7][30]MAIN[7][25]MAIN[6][27]MAIN[7][29]MAIN[7][26]OMUX[7]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][38]MAIN[6][39]MAIN[7][36]MAIN[7][32]MAIN[7][39]MAIN[6][35]MAIN[6][34]MAIN[6][37]OMUX[8]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][33]MAIN[6][32]MAIN[7][35]MAIN[7][33]MAIN[7][38]MAIN[6][36]MAIN[7][34]MAIN[7][37]OMUX[9]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][41]MAIN[6][40]MAIN[7][43]MAIN[7][47]MAIN[7][40]MAIN[6][44]MAIN[6][45]MAIN[6][42]OMUX[10]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][46]MAIN[6][47]MAIN[7][44]MAIN[7][46]MAIN[7][41]MAIN[6][43]MAIN[7][45]MAIN[7][42]OMUX[11]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][54]MAIN[6][55]MAIN[7][52]MAIN[7][48]MAIN[7][55]MAIN[6][51]MAIN[6][50]MAIN[6][53]OMUX[12]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][49]MAIN[6][48]MAIN[7][51]MAIN[7][49]MAIN[7][54]MAIN[6][52]MAIN[7][50]MAIN[7][53]OMUX[13]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][57]MAIN[6][56]MAIN[7][59]MAIN[7][63]MAIN[7][56]MAIN[6][60]MAIN[6][61]MAIN[6][58]OMUX[14]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][62]MAIN[6][63]MAIN[7][60]MAIN[7][62]MAIN[7][57]MAIN[6][59]MAIN[7][61]MAIN[7][58]OMUX[15]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[3]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10010000OUT_FAN[6]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[15]
11010000OUT_FAN[7]
11100000OUT_SEC[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3A_WE switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3A_WE switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3A_WE switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3A_WE switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3A_WE switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[0]
BitsDestination
MAIN[4][23]MAIN[4][22]MAIN[5][23]MAIN[5][16]MAIN[4][18]MAIN[5][20]MAIN[4][19]MAIN[4][21]IMUX_IOCLK[0]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[1]
BitsDestination
MAIN[4][16]MAIN[4][17]MAIN[5][22]MAIN[5][17]MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][21]IMUX_IOCLK[1]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[2]
BitsDestination
MAIN[4][24]MAIN[4][25]MAIN[5][24]MAIN[5][31]MAIN[4][29]MAIN[5][27]MAIN[4][28]MAIN[4][26]IMUX_IOCLK[2]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[3]
BitsDestination
MAIN[4][31]MAIN[4][30]MAIN[5][25]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[4][27]MAIN[5][26]IMUX_IOCLK[3]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[4]
BitsDestination
MAIN[4][39]MAIN[4][38]MAIN[5][39]MAIN[5][32]MAIN[4][34]MAIN[5][36]MAIN[4][35]MAIN[4][37]IMUX_IOCLK[4]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[5]
BitsDestination
MAIN[4][32]MAIN[4][33]MAIN[5][38]MAIN[5][33]MAIN[5][34]MAIN[5][35]MAIN[4][36]MAIN[5][37]IMUX_IOCLK[5]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[6]
BitsDestination
MAIN[4][40]MAIN[4][41]MAIN[5][40]MAIN[5][47]MAIN[4][45]MAIN[5][43]MAIN[4][44]MAIN[4][42]IMUX_IOCLK[6]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_IOCLK[7]
BitsDestination
MAIN[4][47]MAIN[4][46]MAIN[5][41]MAIN[5][46]MAIN[5][45]MAIN[5][44]MAIN[4][43]MAIN[5][42]IMUX_IOCLK[7]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_WE switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_IOI_S3A_WE rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 4 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - - - INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 - INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 7 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 - INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 7 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - - - INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 - INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - - INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - - - INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 4 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_IOCLK[7] bit 7 INT: mux IMUX_IOCLK[6] bit 4 INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 4 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_IOCLK[7] bit 6 INT: mux IMUX_IOCLK[7] bit 4 INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_IOCLK[6] bit 3 INT: mux IMUX_IOCLK[7] bit 3 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_IOCLK[6] bit 1 INT: mux IMUX_IOCLK[7] bit 2 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_IOCLK[7] bit 1 INT: mux IMUX_IOCLK[6] bit 2 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_IOCLK[6] bit 0 INT: mux IMUX_IOCLK[7] bit 0 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_IOCLK[6] bit 6 INT: mux IMUX_IOCLK[7] bit 5 INT: mux OMUX[10] bit 7 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_IOCLK[6] bit 7 INT: mux IMUX_IOCLK[6] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_IOCLK[4] bit 7 INT: mux IMUX_IOCLK[4] bit 5 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 3 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_IOCLK[4] bit 6 INT: mux IMUX_IOCLK[5] bit 5 INT: mux OMUX[8] bit 7 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_IOCLK[4] bit 0 INT: mux IMUX_IOCLK[5] bit 0 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - INT: mux IMUX_IOCLK[5] bit 1 INT: mux IMUX_IOCLK[4] bit 2 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 5 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - INT: mux IMUX_IOCLK[4] bit 1 INT: mux IMUX_IOCLK[5] bit 2 INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - INT: mux IMUX_IOCLK[4] bit 3 INT: mux IMUX_IOCLK[5] bit 3 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - INT: mux IMUX_IOCLK[5] bit 6 INT: mux IMUX_IOCLK[5] bit 4 INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - INT: mux IMUX_IOCLK[5] bit 7 INT: mux IMUX_IOCLK[4] bit 4 INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 4 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - INT: mux IMUX_IOCLK[3] bit 7 INT: mux IMUX_IOCLK[2] bit 4 INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 4 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - INT: mux IMUX_IOCLK[3] bit 6 INT: mux IMUX_IOCLK[3] bit 4 INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - INT: mux IMUX_IOCLK[2] bit 3 INT: mux IMUX_IOCLK[3] bit 3 INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - INT: mux IMUX_IOCLK[2] bit 1 INT: mux IMUX_IOCLK[3] bit 2 INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - INT: mux IMUX_IOCLK[3] bit 1 INT: mux IMUX_IOCLK[2] bit 2 INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 5 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_IOCLK[2] bit 0 INT: mux IMUX_IOCLK[3] bit 0 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_IOCLK[2] bit 6 INT: mux IMUX_IOCLK[3] bit 5 INT: mux OMUX[6] bit 7 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_IOCLK[2] bit 7 INT: mux IMUX_IOCLK[2] bit 5 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 3 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_IOCLK[0] bit 7 INT: mux IMUX_IOCLK[0] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 3 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_IOCLK[0] bit 6 INT: mux IMUX_IOCLK[1] bit 5 INT: mux OMUX[4] bit 7 INT: mux OMUX[5] bit 3 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_IOCLK[0] bit 0 INT: mux IMUX_IOCLK[1] bit 0 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_IOCLK[1] bit 1 INT: mux IMUX_IOCLK[0] bit 2 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_IOCLK[0] bit 1 INT: mux IMUX_IOCLK[1] bit 2 INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[11] bit 3 - INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_IOCLK[0] bit 3 INT: mux IMUX_IOCLK[1] bit 3 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_IOCLK[1] bit 6 INT: mux IMUX_IOCLK[1] bit 4 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 4 - INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_IOCLK[1] bit 7 INT: mux IMUX_IOCLK[0] bit 4 INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 4 - INT: mux IMUX_DATA[22] bit 6 - INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 4 - INT: mux IMUX_DATA[22] bit 5 - INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 4 - - INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - - - INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - - INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 - INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - - - INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 7 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 - INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 7 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 - INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - - - INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - - - INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - - - INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 4 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_IOI_S3A_SN

Used with IOI tiles on Spartan 3A / 3A DSP that are on the top or bottom edge of the device.

Tile INT_IOI_S3A_SN

Cells: 1

Switchbox INT

spartan3 INT_IOI_S3A_SN switchbox INT programmable inverters
DestinationSourceBit
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][6]MAIN[6][7]MAIN[6][3]MAIN[7][0]MAIN[7][7]MAIN[7][4]MAIN[6][2]MAIN[6][5]OMUX[0]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][1]MAIN[6][0]MAIN[6][4]MAIN[7][1]MAIN[7][6]MAIN[7][3]MAIN[7][2]MAIN[7][5]OMUX[1]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][9]MAIN[6][8]MAIN[6][12]MAIN[7][15]MAIN[7][8]MAIN[7][11]MAIN[6][13]MAIN[6][10]OMUX[2]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][14]MAIN[6][15]MAIN[6][11]MAIN[7][14]MAIN[7][9]MAIN[7][12]MAIN[7][13]MAIN[7][10]OMUX[3]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][22]MAIN[6][23]MAIN[6][19]MAIN[7][16]MAIN[7][23]MAIN[7][20]MAIN[6][18]MAIN[6][21]OMUX[4]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][17]MAIN[6][16]MAIN[6][20]MAIN[7][17]MAIN[7][22]MAIN[7][19]MAIN[7][18]MAIN[7][21]OMUX[5]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][25]MAIN[6][24]MAIN[6][28]MAIN[7][31]MAIN[7][24]MAIN[7][27]MAIN[6][29]MAIN[6][26]OMUX[6]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][30]MAIN[6][31]MAIN[6][27]MAIN[7][30]MAIN[7][25]MAIN[7][28]MAIN[7][29]MAIN[7][26]OMUX[7]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][38]MAIN[6][39]MAIN[6][35]MAIN[7][32]MAIN[7][39]MAIN[7][36]MAIN[6][34]MAIN[6][37]OMUX[8]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][33]MAIN[6][32]MAIN[6][36]MAIN[7][33]MAIN[7][38]MAIN[7][35]MAIN[7][34]MAIN[7][37]OMUX[9]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][41]MAIN[6][40]MAIN[6][44]MAIN[7][47]MAIN[7][40]MAIN[7][43]MAIN[6][45]MAIN[6][42]OMUX[10]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][46]MAIN[6][47]MAIN[6][43]MAIN[7][46]MAIN[7][41]MAIN[7][44]MAIN[7][45]MAIN[7][42]OMUX[11]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][54]MAIN[6][55]MAIN[6][51]MAIN[7][48]MAIN[7][55]MAIN[7][52]MAIN[6][50]MAIN[6][53]OMUX[12]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][49]MAIN[6][48]MAIN[6][52]MAIN[7][49]MAIN[7][54]MAIN[7][51]MAIN[7][50]MAIN[7][53]OMUX[13]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][57]MAIN[6][56]MAIN[6][60]MAIN[7][63]MAIN[7][56]MAIN[7][59]MAIN[6][61]MAIN[6][58]OMUX[14]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][62]MAIN[6][63]MAIN[6][59]MAIN[7][62]MAIN[7][57]MAIN[7][60]MAIN[7][61]MAIN[7][58]OMUX[15]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[5]
00010000OUT_SEC[8]
01000001OUT_FAN[0]
01001000OUT_SEC[9]
10000010OUT_SEC[10]
10010000OUT_FAN[6]
11000001OUT_SEC[14]
11000100OUT_SEC[12]
11100000OUT_SEC[13]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_IOI_S3A_SN switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3A_SN switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_IOI_S3A_SN switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_IOI_S3A_SN switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_IOI_S3A_SN switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[0]
BitsDestination
MAIN[4][23]MAIN[4][22]MAIN[5][23]MAIN[5][16]MAIN[4][18]MAIN[5][20]MAIN[4][19]MAIN[4][21]IMUX_IOCLK[0]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[1]
BitsDestination
MAIN[4][16]MAIN[4][17]MAIN[5][22]MAIN[5][17]MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][21]IMUX_IOCLK[1]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[2]
BitsDestination
MAIN[4][24]MAIN[4][25]MAIN[5][24]MAIN[5][31]MAIN[4][29]MAIN[5][27]MAIN[4][28]MAIN[4][26]IMUX_IOCLK[2]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[3]
BitsDestination
MAIN[4][31]MAIN[4][30]MAIN[5][25]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[4][27]MAIN[5][26]IMUX_IOCLK[3]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[4]
BitsDestination
MAIN[4][39]MAIN[4][38]MAIN[5][39]MAIN[5][32]MAIN[4][34]MAIN[5][36]MAIN[4][35]MAIN[4][37]IMUX_IOCLK[4]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[5]
BitsDestination
MAIN[4][32]MAIN[4][33]MAIN[5][38]MAIN[5][33]MAIN[5][34]MAIN[5][35]MAIN[4][36]MAIN[5][37]IMUX_IOCLK[5]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[6]
BitsDestination
MAIN[4][40]MAIN[4][41]MAIN[5][40]MAIN[5][47]MAIN[4][45]MAIN[5][43]MAIN[4][44]MAIN[4][42]IMUX_IOCLK[6]
Source
00000000off
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_IOCLK[7]
BitsDestination
MAIN[4][47]MAIN[4][46]MAIN[5][41]MAIN[5][46]MAIN[5][45]MAIN[5][44]MAIN[4][43]MAIN[5][42]IMUX_IOCLK[7]
Source
00000000PULLUP
00000001HEX_N1[4]
00000010HEX_S4[4]
00000100HEX_N2[4]
00001000HEX_S3[4]
00010000HEX_N0[4]
00100000HEX_S5[4]
01000001GCLK[0]
01000010HEX_N3[4]
01000100HEX_N4[4]
01001000HEX_S1[4]
01010000HEX_S6[4]
01100000DBL_W2[4]
10000001DBL_E0[4]
10000010GCLK[6]
10000100GCLK[7]
10001000DBL_E1[4]
10010000DBL_W1[4]
10100000HEX_N5[4]
11000001GCLK[1]
11000010GCLK[2]
11000100GCLK[3]
11001000GCLK[4]
11010000GCLK[5]
11100000HEX_S2[4]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[0]
00000101DBL_S1[4]
00000110OMUX_WS1
00001101OMUX_SE3
00001110OMUX_W9
00010001DBL_S2[5]
00010010DBL_W1[5]
00011001DBL_N1[4]
00011010DBL_W2[4]
00011101DBL_N1[5]
00011110DBL_N2[5]
00100000IMUX_FAN_BX[1]
00100100DBL_E1[5]
00101100DBL_S2[4]
00110000OMUX_E8
00111000DBL_E1[4]
00111100DBL_S0[4]
01000000DBL_N2[4]
01000100OMUX_N11
01001100DBL_W2[5]
01010000DBL_W0[4]
01011000DBL_E2[4]
01011100OUT_FAN[1]
10000000OUT_FAN[6]
10001100DBL_W1[4]
10010000DBL_E2[5]
10011000DBL_E0[5]
10011100DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_IOI_S3A_SN switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_IOI_S3A_SN rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 4 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 7 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - - - INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 2 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - INT: mux OMUX[14] bit 5 INT: mux OMUX[15] bit 2 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 4 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 - INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 2 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 7 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 5 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 7 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 5 INT: mux OMUX[13] bit 2 - INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 - - INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 4 INT: mux IMUX_DATA[29] bit 7 - INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_IOCLK[7] bit 7 INT: mux IMUX_IOCLK[6] bit 4 INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 4 INT: mux IMUX_DATA[29] bit 5 - INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_IOCLK[7] bit 6 INT: mux IMUX_IOCLK[7] bit 4 INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[29] bit 3 - INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_IOCLK[6] bit 3 INT: mux IMUX_IOCLK[7] bit 3 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 - - INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_IOCLK[6] bit 1 INT: mux IMUX_IOCLK[7] bit 2 INT: mux OMUX[10] bit 5 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_IOCLK[7] bit 1 INT: mux IMUX_IOCLK[6] bit 2 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_IOCLK[6] bit 0 INT: mux IMUX_IOCLK[7] bit 0 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_IOCLK[6] bit 6 INT: mux IMUX_IOCLK[7] bit 5 INT: mux OMUX[10] bit 7 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_IOCLK[6] bit 7 INT: mux IMUX_IOCLK[6] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_IOCLK[4] bit 7 INT: mux IMUX_IOCLK[4] bit 5 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 3 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_IOCLK[4] bit 6 INT: mux IMUX_IOCLK[5] bit 5 INT: mux OMUX[8] bit 7 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_IOCLK[4] bit 0 INT: mux IMUX_IOCLK[5] bit 0 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - INT: mux IMUX_IOCLK[5] bit 1 INT: mux IMUX_IOCLK[4] bit 2 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - INT: mux IMUX_IOCLK[4] bit 1 INT: mux IMUX_IOCLK[5] bit 2 INT: mux OMUX[8] bit 5 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - INT: mux IMUX_IOCLK[4] bit 3 INT: mux IMUX_IOCLK[5] bit 3 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - INT: mux IMUX_IOCLK[5] bit 6 INT: mux IMUX_IOCLK[5] bit 4 INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - INT: mux IMUX_IOCLK[5] bit 7 INT: mux IMUX_IOCLK[4] bit 4 INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 4 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - INT: mux IMUX_IOCLK[3] bit 7 INT: mux IMUX_IOCLK[2] bit 4 INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 4 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - INT: mux IMUX_IOCLK[3] bit 6 INT: mux IMUX_IOCLK[3] bit 4 INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - INT: mux IMUX_IOCLK[2] bit 3 INT: mux IMUX_IOCLK[3] bit 3 INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - INT: mux IMUX_IOCLK[2] bit 1 INT: mux IMUX_IOCLK[3] bit 2 INT: mux OMUX[6] bit 5 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - INT: mux IMUX_IOCLK[3] bit 1 INT: mux IMUX_IOCLK[2] bit 2 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_IOCLK[2] bit 0 INT: mux IMUX_IOCLK[3] bit 0 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_IOCLK[2] bit 6 INT: mux IMUX_IOCLK[3] bit 5 INT: mux OMUX[6] bit 7 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 - INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_IOCLK[2] bit 7 INT: mux IMUX_IOCLK[2] bit 5 INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 3 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 - - INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_IOCLK[0] bit 7 INT: mux IMUX_IOCLK[0] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 3 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 - INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_IOCLK[0] bit 6 INT: mux IMUX_IOCLK[1] bit 5 INT: mux OMUX[4] bit 7 INT: mux OMUX[5] bit 3 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 - INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_IOCLK[0] bit 0 INT: mux IMUX_IOCLK[1] bit 0 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 - - INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_IOCLK[1] bit 1 INT: mux IMUX_IOCLK[0] bit 2 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 2 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_IOCLK[0] bit 1 INT: mux IMUX_IOCLK[1] bit 2 INT: mux OMUX[4] bit 5 INT: mux OMUX[5] bit 2 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_IOCLK[0] bit 3 INT: mux IMUX_IOCLK[1] bit 3 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 - INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_IOCLK[1] bit 6 INT: mux IMUX_IOCLK[1] bit 4 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_IOCLK[1] bit 7 INT: mux IMUX_IOCLK[0] bit 4 INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 4 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 4 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - - - INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - - INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 5 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 - INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 2 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - - - INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 7 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 - INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 7 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 2 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 4 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_BRAM_S3

Used with BRAM_S3 tiles on Spartan 3.

Tile INT_BRAM_S3

Cells: 1

Switchbox INT

spartan3 INT_BRAM_S3 switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[5][63]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][7]MAIN[6][6]MAIN[7][7]MAIN[6][5]MAIN[7][4]MAIN[6][3]MAIN[6][2]MAIN[7][0]OMUX[0]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][0]MAIN[6][1]MAIN[7][6]MAIN[7][5]MAIN[7][3]MAIN[6][4]MAIN[7][2]MAIN[7][1]OMUX[1]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][8]MAIN[6][9]MAIN[7][8]MAIN[6][10]MAIN[7][11]MAIN[6][12]MAIN[6][13]MAIN[7][15]OMUX[2]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][15]MAIN[6][14]MAIN[7][9]MAIN[7][10]MAIN[7][12]MAIN[6][11]MAIN[7][13]MAIN[7][14]OMUX[3]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][23]MAIN[6][22]MAIN[7][23]MAIN[6][21]MAIN[7][20]MAIN[6][19]MAIN[6][18]MAIN[7][16]OMUX[4]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][16]MAIN[6][17]MAIN[7][22]MAIN[7][21]MAIN[7][19]MAIN[6][20]MAIN[7][18]MAIN[7][17]OMUX[5]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][24]MAIN[6][25]MAIN[7][24]MAIN[6][26]MAIN[7][27]MAIN[6][28]MAIN[6][29]MAIN[7][31]OMUX[6]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][31]MAIN[6][30]MAIN[7][25]MAIN[7][26]MAIN[7][28]MAIN[6][27]MAIN[7][29]MAIN[7][30]OMUX[7]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][39]MAIN[6][38]MAIN[7][39]MAIN[6][37]MAIN[7][36]MAIN[6][35]MAIN[6][34]MAIN[7][32]OMUX[8]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][32]MAIN[6][33]MAIN[7][38]MAIN[7][37]MAIN[7][35]MAIN[6][36]MAIN[7][34]MAIN[7][33]OMUX[9]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][40]MAIN[6][41]MAIN[7][40]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][47]OMUX[10]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][47]MAIN[6][46]MAIN[7][41]MAIN[7][42]MAIN[7][44]MAIN[6][43]MAIN[7][45]MAIN[7][46]OMUX[11]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][55]MAIN[6][54]MAIN[7][55]MAIN[6][53]MAIN[7][52]MAIN[6][51]MAIN[6][50]MAIN[7][48]OMUX[12]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][48]MAIN[6][49]MAIN[7][54]MAIN[7][53]MAIN[7][51]MAIN[6][52]MAIN[7][50]MAIN[7][49]OMUX[13]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][56]MAIN[6][57]MAIN[7][56]MAIN[6][58]MAIN[7][59]MAIN[6][60]MAIN[6][61]MAIN[7][63]OMUX[14]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][63]MAIN[6][62]MAIN[7][57]MAIN[7][58]MAIN[7][60]MAIN[6][59]MAIN[7][61]MAIN[7][62]OMUX[15]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3 switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3 switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3 switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3 switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3 switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3 switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3 switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3 switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3 switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][62]MAIN[4][63]MAIN[5][60]MAIN[4][60]MAIN[5][62]MAIN[5][59]IMUX_CE[3]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3 switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_BRAM_S3 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - INT: mux IMUX_CE[3] bit 4 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux OMUX[15] bit 7 INT: mux OMUX[14] bit 0 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[15] bit 6 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - INT: mux IMUX_CE[3] bit 2 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 INT: mux IMUX_CE[3] bit 0 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 6 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - - - INT: mux OMUX[14] bit 7 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - - INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 7 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - - - INT: mux OMUX[12] bit 6 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - - INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 - INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[12] bit 0 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 7 INT: mux OMUX[10] bit 0 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[11] bit 6 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 7 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[8] bit 7 INT: mux OMUX[8] bit 5 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[8] bit 6 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 6 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 3 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 6 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - - - INT: mux OMUX[9] bit 7 INT: mux OMUX[8] bit 0 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[6] bit 0 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - INT: mux OMUX[7] bit 6 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 3 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - - - INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 - INT: mux OMUX[6] bit 6 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - - - INT: mux OMUX[6] bit 7 INT: mux OMUX[6] bit 5 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - - - INT: mux OMUX[4] bit 7 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - - INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - - INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 3 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 - INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 3 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[5] bit 6 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 7 INT: mux OMUX[4] bit 0 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[2] bit 0 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 - INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 - INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 - - - INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 - - INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 6 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 - - - INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 7 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 - - INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 7 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 - - INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 6 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 - - INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 6 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 7 INT: mux OMUX[0] bit 0 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_BRAM_S3E

Used with BRAM_S3E tiles on Spartan 3E.

Tile INT_BRAM_S3E

Cells: 1

Switchbox INT

spartan3 INT_BRAM_S3E switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[5][26]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[5][63]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][7]MAIN[6][6]MAIN[7][7]MAIN[6][5]MAIN[7][4]MAIN[6][3]MAIN[6][2]MAIN[7][0]OMUX[0]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][0]MAIN[6][1]MAIN[7][6]MAIN[7][5]MAIN[7][3]MAIN[6][4]MAIN[7][2]MAIN[7][1]OMUX[1]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][8]MAIN[6][9]MAIN[7][8]MAIN[6][10]MAIN[7][11]MAIN[6][12]MAIN[6][13]MAIN[7][15]OMUX[2]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][15]MAIN[6][14]MAIN[7][9]MAIN[7][10]MAIN[7][12]MAIN[6][11]MAIN[7][13]MAIN[7][14]OMUX[3]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][23]MAIN[6][22]MAIN[7][23]MAIN[6][21]MAIN[7][20]MAIN[6][19]MAIN[6][18]MAIN[7][16]OMUX[4]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][16]MAIN[6][17]MAIN[7][22]MAIN[7][21]MAIN[7][19]MAIN[6][20]MAIN[7][18]MAIN[7][17]OMUX[5]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][24]MAIN[6][25]MAIN[7][24]MAIN[6][26]MAIN[7][27]MAIN[6][28]MAIN[6][29]MAIN[7][31]OMUX[6]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][31]MAIN[6][30]MAIN[7][25]MAIN[7][26]MAIN[7][28]MAIN[6][27]MAIN[7][29]MAIN[7][30]OMUX[7]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][39]MAIN[6][38]MAIN[7][39]MAIN[6][37]MAIN[7][36]MAIN[6][35]MAIN[6][34]MAIN[7][32]OMUX[8]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][32]MAIN[6][33]MAIN[7][38]MAIN[7][37]MAIN[7][35]MAIN[6][36]MAIN[7][34]MAIN[7][33]OMUX[9]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][40]MAIN[6][41]MAIN[7][40]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][47]OMUX[10]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][47]MAIN[6][46]MAIN[7][41]MAIN[7][42]MAIN[7][44]MAIN[6][43]MAIN[7][45]MAIN[7][46]OMUX[11]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][55]MAIN[6][54]MAIN[7][55]MAIN[6][53]MAIN[7][52]MAIN[6][51]MAIN[6][50]MAIN[7][48]OMUX[12]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][48]MAIN[6][49]MAIN[7][54]MAIN[7][53]MAIN[7][51]MAIN[6][52]MAIN[7][50]MAIN[7][49]OMUX[13]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][56]MAIN[6][57]MAIN[7][56]MAIN[6][58]MAIN[7][59]MAIN[6][60]MAIN[6][61]MAIN[7][63]OMUX[14]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][63]MAIN[6][62]MAIN[7][57]MAIN[7][58]MAIN[7][60]MAIN[6][59]MAIN[7][61]MAIN[7][62]OMUX[15]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3E switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3E switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3E switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3E switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3E switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3E switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3E switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3E switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3E switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][24]MAIN[5][25]MAIN[4][24]MAIN[4][26]MAIN[4][21]MAIN[4][23]MAIN[5][23]MAIN[4][20]MAIN[4][16]MAIN[5][19]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][62]MAIN[4][63]MAIN[5][60]MAIN[4][60]MAIN[5][62]MAIN[5][59]IMUX_CE[3]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3E switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_BRAM_S3E rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - INT: mux IMUX_CE[3] bit 4 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux OMUX[15] bit 7 INT: mux OMUX[14] bit 0 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[15] bit 6 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - INT: mux IMUX_CE[3] bit 2 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 INT: mux IMUX_CE[3] bit 0 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 6 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 7 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 7 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 6 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[12] bit 0 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 7 INT: mux OMUX[10] bit 0 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[11] bit 6 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 7 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[8] bit 7 INT: mux OMUX[8] bit 5 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[8] bit 6 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 6 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 3 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 6 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - - - INT: mux OMUX[9] bit 7 INT: mux OMUX[8] bit 0 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[6] bit 0 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - INT: mux OMUX[7] bit 6 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 3 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_CLK[0] bit 6 INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[6] bit 6 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_CLK[0] bit 7 INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[6] bit 7 INT: mux OMUX[6] bit 5 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[0] bit 3 INT: mux OMUX[4] bit 7 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_CLK[0] bit 5 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_CLK[0] bit 2 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 3 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 3 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[5] bit 6 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_CLK[0] bit 1 INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 7 INT: mux OMUX[4] bit 0 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[2] bit 0 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 - INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 - INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 - - - INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 - - INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 6 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 - - - INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 7 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 - - INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 7 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 - - INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 6 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 - - INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 6 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 7 INT: mux OMUX[0] bit 0 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_BRAM_S3A_03

Used with BRAM_S3A tiles on Spartan 3A. This interconnect tile is used in rows 0 and 3 of the BRAM.

Tile INT_BRAM_S3A_03

Cells: 1

Switchbox INT

spartan3 INT_BRAM_S3A_03 switchbox INT programmable inverters
DestinationSourceBit
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][7]MAIN[6][6]MAIN[7][7]MAIN[6][5]MAIN[7][4]MAIN[6][3]MAIN[6][2]MAIN[7][0]OMUX[0]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][0]MAIN[6][1]MAIN[7][6]MAIN[7][5]MAIN[7][3]MAIN[6][4]MAIN[7][2]MAIN[7][1]OMUX[1]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][8]MAIN[6][9]MAIN[7][8]MAIN[6][10]MAIN[7][11]MAIN[6][12]MAIN[6][13]MAIN[7][15]OMUX[2]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][15]MAIN[6][14]MAIN[7][9]MAIN[7][10]MAIN[7][12]MAIN[6][11]MAIN[7][13]MAIN[7][14]OMUX[3]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][23]MAIN[6][22]MAIN[7][23]MAIN[6][21]MAIN[7][20]MAIN[6][19]MAIN[6][18]MAIN[7][16]OMUX[4]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][16]MAIN[6][17]MAIN[7][22]MAIN[7][21]MAIN[7][19]MAIN[6][20]MAIN[7][18]MAIN[7][17]OMUX[5]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][24]MAIN[6][25]MAIN[7][24]MAIN[6][26]MAIN[7][27]MAIN[6][28]MAIN[6][29]MAIN[7][31]OMUX[6]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][31]MAIN[6][30]MAIN[7][25]MAIN[7][26]MAIN[7][28]MAIN[6][27]MAIN[7][29]MAIN[7][30]OMUX[7]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][39]MAIN[6][38]MAIN[7][39]MAIN[6][37]MAIN[7][36]MAIN[6][35]MAIN[6][34]MAIN[7][32]OMUX[8]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][32]MAIN[6][33]MAIN[7][38]MAIN[7][37]MAIN[7][35]MAIN[6][36]MAIN[7][34]MAIN[7][33]OMUX[9]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][40]MAIN[6][41]MAIN[7][40]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][47]OMUX[10]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][47]MAIN[6][46]MAIN[7][41]MAIN[7][42]MAIN[7][44]MAIN[6][43]MAIN[7][45]MAIN[7][46]OMUX[11]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][55]MAIN[6][54]MAIN[7][55]MAIN[6][53]MAIN[7][52]MAIN[6][51]MAIN[6][50]MAIN[7][48]OMUX[12]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][48]MAIN[6][49]MAIN[7][54]MAIN[7][53]MAIN[7][51]MAIN[6][52]MAIN[7][50]MAIN[7][49]OMUX[13]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][56]MAIN[6][57]MAIN[7][56]MAIN[6][58]MAIN[7][59]MAIN[6][60]MAIN[6][61]MAIN[7][63]OMUX[14]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][63]MAIN[6][62]MAIN[7][57]MAIN[7][58]MAIN[7][60]MAIN[6][59]MAIN[7][61]MAIN[7][62]OMUX[15]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_03 switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_BRAM_S3A_03 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - INT: mux OMUX[15] bit 7 INT: mux OMUX[14] bit 0 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - - - INT: mux OMUX[15] bit 6 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - - - INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - - - INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - - - INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - - - INT: mux OMUX[14] bit 6 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - - - INT: mux OMUX[14] bit 7 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - - - INT: mux OMUX[12] bit 7 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - - - INT: mux OMUX[12] bit 6 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - - - INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - - - INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - - - INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - - - INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[12] bit 0 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - - - INT: mux OMUX[11] bit 7 INT: mux OMUX[10] bit 0 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - - - INT: mux OMUX[11] bit 6 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - - - INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - - - INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - - - INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - - - INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - - - INT: mux OMUX[10] bit 6 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - - - INT: mux OMUX[10] bit 7 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - - - INT: mux OMUX[8] bit 7 INT: mux OMUX[8] bit 5 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - - - INT: mux OMUX[8] bit 6 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - - - INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 3 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 6 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - - - INT: mux OMUX[9] bit 7 INT: mux OMUX[8] bit 0 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[6] bit 0 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - INT: mux OMUX[7] bit 6 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 3 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - - - INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - - - INT: mux OMUX[6] bit 6 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - - - INT: mux OMUX[6] bit 7 INT: mux OMUX[6] bit 5 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - - - INT: mux OMUX[4] bit 7 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - - - INT: mux OMUX[4] bit 6 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - - - INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - - - INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 3 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - - - INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 3 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - - - INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - - - INT: mux OMUX[5] bit 6 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - - - INT: mux OMUX[5] bit 7 INT: mux OMUX[4] bit 0 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[2] bit 0 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 6 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 7 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 7 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 6 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 6 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 7 INT: mux OMUX[0] bit 0 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_BRAM_S3A_12

Used with BRAM_S3A tiles on Spartan 3A. This interconnect tile is used in rows 1 and 2 of the BRAM.

Tile INT_BRAM_S3A_12

Cells: 1

Switchbox INT

spartan3 INT_BRAM_S3A_12 switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[5][26]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[5][63]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][7]MAIN[6][6]MAIN[7][7]MAIN[6][5]MAIN[7][4]MAIN[6][3]MAIN[6][2]MAIN[7][0]OMUX[0]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][0]MAIN[6][1]MAIN[7][6]MAIN[7][5]MAIN[7][3]MAIN[6][4]MAIN[7][2]MAIN[7][1]OMUX[1]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][8]MAIN[6][9]MAIN[7][8]MAIN[6][10]MAIN[7][11]MAIN[6][12]MAIN[6][13]MAIN[7][15]OMUX[2]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][15]MAIN[6][14]MAIN[7][9]MAIN[7][10]MAIN[7][12]MAIN[6][11]MAIN[7][13]MAIN[7][14]OMUX[3]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][23]MAIN[6][22]MAIN[7][23]MAIN[6][21]MAIN[7][20]MAIN[6][19]MAIN[6][18]MAIN[7][16]OMUX[4]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][16]MAIN[6][17]MAIN[7][22]MAIN[7][21]MAIN[7][19]MAIN[6][20]MAIN[7][18]MAIN[7][17]OMUX[5]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][24]MAIN[6][25]MAIN[7][24]MAIN[6][26]MAIN[7][27]MAIN[6][28]MAIN[6][29]MAIN[7][31]OMUX[6]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][31]MAIN[6][30]MAIN[7][25]MAIN[7][26]MAIN[7][28]MAIN[6][27]MAIN[7][29]MAIN[7][30]OMUX[7]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][39]MAIN[6][38]MAIN[7][39]MAIN[6][37]MAIN[7][36]MAIN[6][35]MAIN[6][34]MAIN[7][32]OMUX[8]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][32]MAIN[6][33]MAIN[7][38]MAIN[7][37]MAIN[7][35]MAIN[6][36]MAIN[7][34]MAIN[7][33]OMUX[9]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][40]MAIN[6][41]MAIN[7][40]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][47]OMUX[10]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][47]MAIN[6][46]MAIN[7][41]MAIN[7][42]MAIN[7][44]MAIN[6][43]MAIN[7][45]MAIN[7][46]OMUX[11]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][55]MAIN[6][54]MAIN[7][55]MAIN[6][53]MAIN[7][52]MAIN[6][51]MAIN[6][50]MAIN[7][48]OMUX[12]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][48]MAIN[6][49]MAIN[7][54]MAIN[7][53]MAIN[7][51]MAIN[6][52]MAIN[7][50]MAIN[7][49]OMUX[13]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][56]MAIN[6][57]MAIN[7][56]MAIN[6][58]MAIN[7][59]MAIN[6][60]MAIN[6][61]MAIN[7][63]OMUX[14]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][63]MAIN[6][62]MAIN[7][57]MAIN[7][58]MAIN[7][60]MAIN[6][59]MAIN[7][61]MAIN[7][62]OMUX[15]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][24]MAIN[5][25]MAIN[4][24]MAIN[4][26]MAIN[4][21]MAIN[4][23]MAIN[5][23]MAIN[4][20]MAIN[4][16]MAIN[5][19]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][62]MAIN[4][63]MAIN[5][60]MAIN[4][60]MAIN[5][62]MAIN[5][59]IMUX_CE[3]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3A_12 switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_BRAM_S3A_12 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - INT: mux IMUX_CE[3] bit 4 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux OMUX[15] bit 7 INT: mux OMUX[14] bit 0 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[15] bit 6 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - INT: mux IMUX_CE[3] bit 2 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 INT: mux IMUX_CE[3] bit 0 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 6 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 7 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 7 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 6 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[12] bit 0 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 7 INT: mux OMUX[10] bit 0 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[11] bit 6 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 7 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[8] bit 7 INT: mux OMUX[8] bit 5 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[8] bit 6 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 6 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 3 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 6 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - - - INT: mux OMUX[9] bit 7 INT: mux OMUX[8] bit 0 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[6] bit 0 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - INT: mux OMUX[7] bit 6 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 3 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_CLK[0] bit 6 INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[6] bit 6 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_CLK[0] bit 7 INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[6] bit 7 INT: mux OMUX[6] bit 5 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[0] bit 3 INT: mux OMUX[4] bit 7 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_CLK[0] bit 5 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_CLK[0] bit 2 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 3 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 3 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[5] bit 6 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_CLK[0] bit 1 INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 7 INT: mux OMUX[4] bit 0 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[2] bit 0 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 6 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 7 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 7 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 6 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 6 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 7 INT: mux OMUX[0] bit 0 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_BRAM_S3ADSP

Used with BRAM_S3ADSP or DSP tiles on Spartan 3A DSP.

Tile INT_BRAM_S3ADSP

Cells: 1

Switchbox INT

spartan3 INT_BRAM_S3ADSP switchbox INT permanent buffers
DestinationSource
IMUX_FAN_BX_BOUNCE[0]IMUX_FAN_BX[0]
IMUX_FAN_BX_BOUNCE[1]IMUX_FAN_BX[1]
IMUX_FAN_BX_BOUNCE[2]IMUX_FAN_BX[2]
IMUX_FAN_BX_BOUNCE[3]IMUX_FAN_BX[3]
IMUX_FAN_BY_BOUNCE[0]IMUX_FAN_BY[0]
IMUX_FAN_BY_BOUNCE[1]IMUX_FAN_BY[1]
IMUX_FAN_BY_BOUNCE[2]IMUX_FAN_BY[2]
IMUX_FAN_BY_BOUNCE[3]IMUX_FAN_BY[3]
spartan3 INT_BRAM_S3ADSP switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[5][26]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[5][6]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[5][7]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[5][0]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[5][13]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[5][56]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[5][57]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[5][50]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[5][63]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][7]MAIN[6][6]MAIN[7][7]MAIN[6][5]MAIN[7][4]MAIN[6][3]MAIN[6][2]MAIN[7][0]OMUX[0]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][0]MAIN[6][1]MAIN[7][6]MAIN[7][5]MAIN[7][3]MAIN[6][4]MAIN[7][2]MAIN[7][1]OMUX[1]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][8]MAIN[6][9]MAIN[7][8]MAIN[6][10]MAIN[7][11]MAIN[6][12]MAIN[6][13]MAIN[7][15]OMUX[2]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][15]MAIN[6][14]MAIN[7][9]MAIN[7][10]MAIN[7][12]MAIN[6][11]MAIN[7][13]MAIN[7][14]OMUX[3]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][23]MAIN[6][22]MAIN[7][23]MAIN[6][21]MAIN[7][20]MAIN[6][19]MAIN[6][18]MAIN[7][16]OMUX[4]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][16]MAIN[6][17]MAIN[7][22]MAIN[7][21]MAIN[7][19]MAIN[6][20]MAIN[7][18]MAIN[7][17]OMUX[5]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][24]MAIN[6][25]MAIN[7][24]MAIN[6][26]MAIN[7][27]MAIN[6][28]MAIN[6][29]MAIN[7][31]OMUX[6]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][31]MAIN[6][30]MAIN[7][25]MAIN[7][26]MAIN[7][28]MAIN[6][27]MAIN[7][29]MAIN[7][30]OMUX[7]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF0[1]
01001000OUT_HALF0[0]
01010000OUT_HALF0[2]
01100000OUT_HALF0[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][39]MAIN[6][38]MAIN[7][39]MAIN[6][37]MAIN[7][36]MAIN[6][35]MAIN[6][34]MAIN[7][32]OMUX[8]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][32]MAIN[6][33]MAIN[7][38]MAIN[7][37]MAIN[7][35]MAIN[6][36]MAIN[7][34]MAIN[7][33]OMUX[9]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][40]MAIN[6][41]MAIN[7][40]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][47]OMUX[10]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][47]MAIN[6][46]MAIN[7][41]MAIN[7][42]MAIN[7][44]MAIN[6][43]MAIN[7][45]MAIN[7][46]OMUX[11]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][55]MAIN[6][54]MAIN[7][55]MAIN[6][53]MAIN[7][52]MAIN[6][51]MAIN[6][50]MAIN[7][48]OMUX[12]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][48]MAIN[6][49]MAIN[7][54]MAIN[7][53]MAIN[7][51]MAIN[6][52]MAIN[7][50]MAIN[7][49]OMUX[13]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][56]MAIN[6][57]MAIN[7][56]MAIN[6][58]MAIN[7][59]MAIN[6][60]MAIN[6][61]MAIN[7][63]OMUX[14]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][63]MAIN[6][62]MAIN[7][57]MAIN[7][58]MAIN[7][60]MAIN[6][59]MAIN[7][61]MAIN[7][62]OMUX[15]
Source
00000000off
00000001OUT_FAN[0]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[4]
00100000OUT_FAN[5]
01000001OUT_FAN[6]
01000010OUT_FAN[7]
01000100OUT_HALF1[1]
01001000OUT_HALF1[0]
01010000OUT_HALF1[2]
01100000OUT_HALF1[3]
10000001OUT_SEC[4]
10000010OUT_SEC[5]
10000100OUT_SEC[7]
10010000OUT_SEC[8]
10100000OUT_SEC[9]
11000001OUT_SEC[10]
11000010OUT_SEC[11]
11000100OUT_SEC[13]
11001000OUT_SEC[12]
11010000OUT_SEC[14]
11100000OUT_SEC[15]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][24]MAIN[5][25]MAIN[4][24]MAIN[4][26]MAIN[4][21]MAIN[4][23]MAIN[5][23]MAIN[4][20]MAIN[4][16]MAIN[5][19]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[4][6]MAIN[4][5]MAIN[4][4]MAIN[5][5]MAIN[4][2]MAIN[5][2]IMUX_SR[0]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][7]MAIN[4][8]MAIN[4][9]MAIN[5][9]MAIN[5][12]MAIN[4][11]IMUX_SR[1]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][1]MAIN[5][4]MAIN[4][3]MAIN[5][3]MAIN[5][1]IMUX_SR[2]
Source
000000PULLUP
000001DBL_E1[0]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[0]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[0]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[0]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[4][13]MAIN[4][12]MAIN[5][8]MAIN[4][10]MAIN[5][10]MAIN[5][11]IMUX_SR[3]
Source
000000PULLUP
000001DBL_E1[1]
000010HEX_S4[0]
000100HEX_S5[0]
001000HEX_S6[0]
010001DBL_W1[1]
010010HEX_N0[0]
010100HEX_N1[0]
011000HEX_N2[0]
100001DBL_E0[1]
100010HEX_S1[0]
100100HEX_S2[0]
101000HEX_S3[0]
110001DBL_W2[1]
110010HEX_N3[0]
110100HEX_N4[0]
111000HEX_N5[0]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[4][55]MAIN[4][56]MAIN[5][51]MAIN[5][54]MAIN[4][54]MAIN[4][52]IMUX_CE[0]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][58]MAIN[4][57]MAIN[4][61]MAIN[5][58]MAIN[5][61]MAIN[4][59]IMUX_CE[1]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[4][51]MAIN[4][50]MAIN[5][53]MAIN[4][53]MAIN[5][55]MAIN[5][52]IMUX_CE[2]
Source
000000PULLUP
000001DBL_W2[6]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W1[6]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E1[6]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E0[6]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][62]MAIN[4][63]MAIN[5][60]MAIN[4][60]MAIN[5][62]MAIN[5][59]IMUX_CE[3]
Source
000000PULLUP
000001DBL_W1[7]
000010HEX_N5[7]
000100HEX_N4[7]
001000HEX_N3[7]
010001DBL_W2[7]
010010HEX_N2[7]
010100HEX_N1[7]
011000HEX_N0[7]
100001DBL_E0[7]
100010HEX_S4[7]
100100HEX_S5[7]
101000HEX_S6[7]
110001DBL_E1[7]
110010HEX_S1[7]
110100HEX_S2[7]
111000HEX_S3[7]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BX[1]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BX[3]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BY[1]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BY[3]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[0]
BitsDestination
MAIN[9][42]MAIN[9][40]MAIN[9][41]MAIN[10][43]MAIN[8][45]MAIN[9][39]MAIN[8][39]MAIN[10][39]IMUX_DATA[0]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[1]
BitsDestination
MAIN[12][10]MAIN[12][8]MAIN[12][9]MAIN[11][7]MAIN[11][12]MAIN[10][11]MAIN[10][9]MAIN[12][11]IMUX_DATA[1]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[4]
BitsDestination
MAIN[8][1]MAIN[8][2]MAIN[8][3]MAIN[8][4]MAIN[10][2]MAIN[9][0]MAIN[10][6]MAIN[9][4]IMUX_DATA[4]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[5]
BitsDestination
MAIN[11][48]MAIN[11][47]MAIN[11][46]MAIN[11][45]MAIN[12][51]MAIN[11][50]MAIN[12][50]MAIN[10][44]IMUX_DATA[5]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[6]
BitsDestination
MAIN[8][14]MAIN[8][16]MAIN[8][15]MAIN[8][17]MAIN[10][15]MAIN[9][14]MAIN[9][19]MAIN[10][16]IMUX_DATA[6]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[7]
BitsDestination
MAIN[11][60]MAIN[11][61]MAIN[11][62]MAIN[11][58]MAIN[12][63]MAIN[10][63]MAIN[12][58]MAIN[10][58]IMUX_DATA[7]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[8]
BitsDestination
MAIN[11][42]MAIN[11][41]MAIN[11][40]MAIN[11][39]MAIN[12][45]MAIN[10][42]MAIN[12][39]MAIN[10][38]IMUX_DATA[8]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[9]
BitsDestination
MAIN[8][10]MAIN[8][8]MAIN[8][9]MAIN[8][11]MAIN[10][8]MAIN[9][7]MAIN[9][12]MAIN[10][10]IMUX_DATA[9]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[10]
BitsDestination
MAIN[11][54]MAIN[11][55]MAIN[11][53]MAIN[11][52]MAIN[12][57]MAIN[11][57]MAIN[12][56]MAIN[10][50]IMUX_DATA[10]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[11]
BitsDestination
MAIN[8][20]MAIN[8][22]MAIN[8][21]MAIN[8][23]MAIN[8][19]MAIN[9][20]MAIN[9][25]MAIN[10][22]IMUX_DATA[11]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[12]
BitsDestination
MAIN[12][1]MAIN[12][2]MAIN[12][3]MAIN[11][0]MAIN[10][7]MAIN[11][4]MAIN[10][3]MAIN[12][4]IMUX_DATA[12]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[13]
BitsDestination
MAIN[9][48]MAIN[9][46]MAIN[9][47]MAIN[9][50]MAIN[8][51]MAIN[9][45]MAIN[8][50]MAIN[10][45]IMUX_DATA[13]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[14]
BitsDestination
MAIN[12][14]MAIN[12][16]MAIN[12][15]MAIN[11][14]MAIN[11][19]MAIN[10][17]MAIN[10][14]MAIN[12][17]IMUX_DATA[14]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[15]
BitsDestination
MAIN[9][60]MAIN[9][62]MAIN[9][61]MAIN[10][62]MAIN[8][63]MAIN[9][58]MAIN[8][58]MAIN[10][59]IMUX_DATA[15]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX_BOUNCE[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX_BOUNCE[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX_BOUNCE[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX_BOUNCE[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY_BOUNCE[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY_BOUNCE[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_BRAM_S3ADSP switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY_BOUNCE[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY_BOUNCE[3]
11110000DBL_S0[6]

Bitstream

spartan3 INT_BRAM_S3ADSP rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - INT: mux IMUX_CE[3] bit 4 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux OMUX[15] bit 7 INT: mux OMUX[14] bit 0 INT: mux IMUX_DATA[15] bit 3 INT: mux IMUX_DATA[31] bit 2 INT: mux IMUX_DATA[7] bit 2 INT: mux IMUX_DATA[23] bit 4 INT: mux IMUX_DATA[7] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[15] bit 6 INT: mux OMUX[15] bit 0 INT: mux IMUX_DATA[31] bit 6 INT: mux IMUX_DATA[15] bit 6 INT: mux IMUX_DATA[15] bit 4 INT: mux IMUX_DATA[7] bit 5 INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - INT: mux IMUX_CE[1] bit 3 INT: mux IMUX_CE[1] bit 1 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 INT: mux IMUX_DATA[15] bit 5 INT: mux IMUX_DATA[31] bit 1 INT: mux IMUX_DATA[7] bit 6 INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - INT: mux IMUX_CE[3] bit 2 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 3 INT: mux IMUX_DATA[31] bit 7 INT: mux IMUX_DATA[15] bit 7 INT: mux IMUX_DATA[23] bit 1 INT: mux IMUX_DATA[7] bit 7 INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - INT: mux IMUX_CE[1] bit 0 INT: mux IMUX_CE[3] bit 0 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 3 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 INT: mux IMUX_DATA[15] bit 0 INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[15] bit 1 INT: mux IMUX_DATA[15] bit 2 INT: mux IMUX_DATA[7] bit 0 INT: mux IMUX_DATA[7] bit 4 INT: mux IMUX_DATA[7] bit 1 INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - INT: mux IMUX_CE[1] bit 4 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux OMUX[14] bit 6 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 INT: mux IMUX_DATA[10] bit 2 INT: mux IMUX_DATA[10] bit 3 INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - INT: mux IMUX_CE[0] bit 4 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux OMUX[14] bit 7 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 INT: mux IMUX_DATA[10] bit 1 INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[12] bit 7 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 INT: mux IMUX_DATA[10] bit 6 INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 6 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 INT: mux IMUX_DATA[10] bit 7 INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - INT: mux IMUX_CE[2] bit 2 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 INT: mux IMUX_DATA[10] bit 5 INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[2] bit 0 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 3 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 INT: mux IMUX_DATA[10] bit 4 INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 3 INT: mux IMUX_DATA[13] bit 3 INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 INT: mux IMUX_DATA[5] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - INT: mux IMUX_CE[2] bit 4 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_DATA[13] bit 1 INT: mux IMUX_DATA[13] bit 4 INT: mux IMUX_DATA[10] bit 0 INT: mux IMUX_DATA[5] bit 2 INT: mux IMUX_DATA[5] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - INT: mux OMUX[13] bit 6 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - INT: mux OMUX[13] bit 7 INT: mux OMUX[12] bit 0 INT: mux IMUX_DATA[29] bit 7 INT: mux IMUX_DATA[13] bit 7 INT: mux IMUX_DATA[29] bit 1 INT: mux IMUX_DATA[5] bit 7 INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 7 INT: mux OMUX[10] bit 0 INT: mux IMUX_DATA[29] bit 5 INT: mux IMUX_DATA[13] bit 5 INT: mux IMUX_DATA[29] bit 0 INT: mux IMUX_DATA[5] bit 6 INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[11] bit 6 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[29] bit 3 INT: mux IMUX_DATA[13] bit 6 INT: mux IMUX_DATA[21] bit 0 INT: mux IMUX_DATA[5] bit 5 INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_DATA[0] bit 3 INT: mux IMUX_DATA[13] bit 2 INT: mux IMUX_DATA[13] bit 0 INT: mux IMUX_DATA[5] bit 4 INT: mux IMUX_DATA[8] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 3 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 INT: mux IMUX_DATA[5] bit 0 INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 3 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 INT: mux IMUX_DATA[0] bit 4 INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 7 INT: mux IMUX_DATA[0] bit 7 INT: mux IMUX_DATA[8] bit 2 INT: mux IMUX_DATA[8] bit 7 INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 6 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[16] bit 5 INT: mux IMUX_DATA[0] bit 5 INT: mux IMUX_DATA[16] bit 0 INT: mux IMUX_DATA[8] bit 6 INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 7 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[16] bit 3 INT: mux IMUX_DATA[0] bit 6 INT: mux IMUX_DATA[24] bit 0 INT: mux IMUX_DATA[8] bit 5 INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[8] bit 7 INT: mux OMUX[8] bit 5 INT: mux IMUX_DATA[0] bit 1 INT: mux IMUX_DATA[0] bit 2 INT: mux IMUX_DATA[0] bit 0 INT: mux IMUX_DATA[8] bit 4 INT: mux IMUX_DATA[8] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[8] bit 6 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux IMUX_DATA[16] bit 4 INT: mux IMUX_DATA[8] bit 0 INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 6 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 3 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 3 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 6 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - - - INT: mux OMUX[9] bit 7 INT: mux OMUX[8] bit 0 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[6] bit 0 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - INT: mux OMUX[7] bit 6 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 3 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 3 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - INT: mux IMUX_CLK[0] bit 6 INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[6] bit 6 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[0] bit 3 INT: mux IMUX_DATA[11] bit 1 INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - INT: mux IMUX_CLK[0] bit 7 INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[6] bit 7 INT: mux OMUX[6] bit 5 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[0] bit 3 INT: mux OMUX[4] bit 7 INT: mux OMUX[4] bit 5 INT: mux IMUX_DATA[11] bit 4 INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[4] bit 6 INT: mux OMUX[5] bit 5 INT: mux IMUX_DATA[11] bit 6 INT: mux IMUX_DATA[27] bit 6 INT: mux IMUX_DATA[11] bit 0 INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - - INT: mux IMUX_CLK[0] bit 5 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_DATA[11] bit 5 INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - INT: mux IMUX_CLK[0] bit 2 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 3 INT: mux IMUX_DATA[11] bit 7 INT: mux IMUX_DATA[11] bit 2 INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 3 INT: mux IMUX_DATA[11] bit 3 INT: mux IMUX_DATA[6] bit 1 INT: mux IMUX_DATA[30] bit 2 INT: mux IMUX_DATA[14] bit 3 INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - - INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[5] bit 6 INT: mux OMUX[5] bit 0 INT: mux IMUX_DATA[6] bit 4 INT: mux IMUX_DATA[22] bit 7 INT: mux IMUX_DATA[14] bit 2 INT: mux IMUX_DATA[30] bit 7 INT: mux IMUX_DATA[14] bit 0 INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - - INT: mux IMUX_CLK[0] bit 1 INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 7 INT: mux OMUX[4] bit 0 INT: mux IMUX_DATA[6] bit 6 INT: mux IMUX_DATA[22] bit 6 INT: mux IMUX_DATA[6] bit 0 INT: mux IMUX_DATA[30] bit 6 INT: mux IMUX_DATA[14] bit 6 INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[2] bit 0 INT: mux IMUX_DATA[6] bit 5 INT: mux IMUX_DATA[22] bit 5 INT: mux IMUX_DATA[6] bit 3 INT: mux IMUX_DATA[30] bit 5 INT: mux IMUX_DATA[14] bit 5 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[3] bit 0 INT: mux IMUX_DATA[6] bit 7 INT: mux IMUX_DATA[6] bit 2 INT: mux IMUX_DATA[14] bit 1 INT: mux IMUX_DATA[14] bit 4 INT: mux IMUX_DATA[14] bit 7 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - INT: mux IMUX_SR[3] bit 5 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 3 INT: mux IMUX_DATA[22] bit 4 INT: mux IMUX_DATA[9] bit 1 INT: mux IMUX_DATA[25] bit 0 INT: mux IMUX_DATA[1] bit 3 INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 3 INT: mux IMUX_DATA[9] bit 4 INT: mux IMUX_DATA[25] bit 2 INT: mux IMUX_DATA[1] bit 2 INT: mux IMUX_DATA[17] bit 4 INT: mux IMUX_DATA[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - INT: mux IMUX_SR[3] bit 2 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_DATA[9] bit 7 INT: mux IMUX_DATA[25] bit 7 INT: mux IMUX_DATA[9] bit 0 INT: mux IMUX_DATA[17] bit 7 INT: mux IMUX_DATA[1] bit 7 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[2] bit 6 INT: mux OMUX[3] bit 5 INT: mux IMUX_DATA[9] bit 5 INT: mux IMUX_DATA[25] bit 5 INT: mux IMUX_DATA[1] bit 1 INT: mux IMUX_DATA[17] bit 5 INT: mux IMUX_DATA[1] bit 5 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 7 INT: mux OMUX[2] bit 5 INT: mux IMUX_DATA[9] bit 6 INT: mux IMUX_DATA[25] bit 6 INT: mux IMUX_DATA[9] bit 3 INT: mux IMUX_DATA[17] bit 6 INT: mux IMUX_DATA[1] bit 6 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - INT: mux IMUX_SR[1] bit 5 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux OMUX[0] bit 7 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[25] bit 3 INT: mux IMUX_DATA[9] bit 2 INT: mux IMUX_DATA[12] bit 3 INT: mux IMUX_DATA[1] bit 4 INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - INT: mux IMUX_SR[0] bit 5 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux OMUX[0] bit 6 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 INT: mux IMUX_DATA[4] bit 1 INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 3 INT: mux IMUX_DATA[4] bit 4 INT: mux IMUX_DATA[4] bit 0 INT: mux IMUX_DATA[20] bit 0 INT: mux IMUX_DATA[12] bit 2 INT: mux IMUX_DATA[12] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - INT: mux IMUX_SR[2] bit 2 INT: mux IMUX_SR[2] bit 1 INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 3 INT: mux IMUX_DATA[4] bit 5 INT: mux IMUX_DATA[20] bit 5 INT: mux IMUX_DATA[12] bit 1 INT: mux IMUX_DATA[28] bit 5 INT: mux IMUX_DATA[12] bit 5 INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_DATA[4] bit 6 INT: mux IMUX_DATA[20] bit 6 INT: mux IMUX_DATA[4] bit 3 INT: mux IMUX_DATA[28] bit 6 INT: mux IMUX_DATA[12] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - INT: mux IMUX_SR[2] bit 4 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[1] bit 6 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[4] bit 7 INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 INT: mux IMUX_DATA[12] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - INT: mux IMUX_SR[2] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux OMUX[1] bit 7 INT: mux OMUX[0] bit 0 INT: mux IMUX_DATA[20] bit 4 INT: mux IMUX_DATA[4] bit 2 INT: mux IMUX_DATA[28] bit 3 INT: mux IMUX_DATA[12] bit 4 INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_DCM

Used with DCM_* tiles.

Tile INT_DCM

Cells: 1

Switchbox INT

spartan3 INT_DCM switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
spartan3 INT_DCM switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][6]MAIN[6][7]MAIN[7][0]MAIN[7][7]MAIN[6][3]MAIN[7][4]MAIN[6][2]MAIN[6][5]OMUX[0]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][1]MAIN[6][0]MAIN[7][1]MAIN[7][6]MAIN[6][4]MAIN[7][3]MAIN[7][2]MAIN[7][5]OMUX[1]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][9]MAIN[6][8]MAIN[7][15]MAIN[7][8]MAIN[6][12]MAIN[7][11]MAIN[6][13]MAIN[6][10]OMUX[2]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][14]MAIN[6][15]MAIN[7][14]MAIN[7][9]MAIN[6][11]MAIN[7][12]MAIN[7][13]MAIN[7][10]OMUX[3]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][22]MAIN[6][23]MAIN[7][16]MAIN[7][23]MAIN[6][19]MAIN[7][20]MAIN[6][18]MAIN[6][21]OMUX[4]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][17]MAIN[6][16]MAIN[7][17]MAIN[7][22]MAIN[6][20]MAIN[7][19]MAIN[7][18]MAIN[7][21]OMUX[5]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][25]MAIN[6][24]MAIN[7][31]MAIN[7][24]MAIN[6][28]MAIN[7][27]MAIN[6][29]MAIN[6][26]OMUX[6]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][30]MAIN[6][31]MAIN[7][30]MAIN[7][25]MAIN[6][27]MAIN[7][28]MAIN[7][29]MAIN[7][26]OMUX[7]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][38]MAIN[6][39]MAIN[7][32]MAIN[7][39]MAIN[6][35]MAIN[7][36]MAIN[6][34]MAIN[6][37]OMUX[8]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][33]MAIN[6][32]MAIN[7][33]MAIN[7][38]MAIN[6][36]MAIN[7][35]MAIN[7][34]MAIN[7][37]OMUX[9]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][41]MAIN[6][40]MAIN[7][47]MAIN[7][40]MAIN[6][44]MAIN[7][43]MAIN[6][45]MAIN[6][42]OMUX[10]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][46]MAIN[6][47]MAIN[7][46]MAIN[7][41]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[7][42]OMUX[11]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][54]MAIN[6][55]MAIN[7][48]MAIN[7][55]MAIN[6][51]MAIN[7][52]MAIN[6][50]MAIN[6][53]OMUX[12]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][49]MAIN[6][48]MAIN[7][49]MAIN[7][54]MAIN[6][52]MAIN[7][51]MAIN[7][50]MAIN[7][53]OMUX[13]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][57]MAIN[6][56]MAIN[7][63]MAIN[7][56]MAIN[6][60]MAIN[7][59]MAIN[6][61]MAIN[6][58]OMUX[14]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][62]MAIN[6][63]MAIN[7][62]MAIN[7][57]MAIN[6][59]MAIN[7][60]MAIN[7][61]MAIN[7][58]OMUX[15]
Source
00000000off
00000001OUT_FAN[4]
00000010OUT_FAN[1]
00000100OUT_FAN[2]
00001000OUT_FAN[3]
00010000OUT_FAN[5]
00100000OUT_SEC[8]
01000001OUT_FAN[0]
01000010OUT_SEC[5]
01000100OUT_SEC[6]
01001000OUT_SEC[7]
01010000OUT_SEC[9]
01100000OUT_SEC[4]
10000001OUT_SEC[2]
10000010OUT_SEC[10]
10000100OUT_SEC[0]
10001000OUT_SEC[1]
10010000OUT_SEC[3]
10100000OUT_FAN[6]
11000001OUT_SEC[14]
11000010OUT_SEC[11]
11000100OUT_SEC[12]
11001000OUT_SEC[13]
11010000OUT_SEC[15]
11100000OUT_FAN[7]
spartan3 INT_DCM switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_DCM switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_DCM switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_DCM switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_DCM switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_DCM switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000001OUT_FAN[0]
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[6]
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_DCM switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000010OUT_FAN[3]
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010010OUT_FAN[4]
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_DCM switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
001000OUT_FAN[2]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
011000OUT_FAN[5]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_DCM switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001OUT_FAN[3]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
001000OUT_FAN[4]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
011000OUT_FAN[2]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_DCM switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010010OUT_FAN[6]
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_DCM switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
001000OUT_FAN[1]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
011000OUT_FAN[7]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_DCM switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_DCM switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_DCM switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_DCM switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_DCM switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_DCM switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_DCM switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_DCM switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_DCM switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000001OUT_FAN[3]
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_DCM switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100OUT_FAN[2]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
010100OUT_FAN[4]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_DCM switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OUT_FAN[5]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_DCM switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100OUT_FAN[4]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
010100OUT_FAN[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_DCM switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000010OUT_FAN[5]
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010010OUT_FAN[2]
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_DCM switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100OUT_FAN[1]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
010100OUT_FAN[6]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_DCM switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000010OUT_FAN[0]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010010OUT_FAN[7]
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_DCM switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000001OUT_FAN[6]
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_NW10
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_W1
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_NW10
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_N12
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_WN14
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00001OUT_FAN[0]
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00010OUT_FAN[6]
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_DCM switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
00100OUT_FAN[3]
01001OMUX_E2
01010HEX_N7[7]
01100OUT_FAN[4]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
00100OUT_FAN[2]
01001OMUX_S4
01010HEX_S3[1]
01100OUT_FAN[5]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01001OUT_FAN[3]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_DCM switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
00100OUT_FAN[4]
01001OMUX_SE3
01010HEX_S3[3]
01100OUT_FAN[2]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
00100OUT_FAN[5]
01001OMUX_E8
01010HEX_N6[3]
01100OUT_FAN[6]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_DCM switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
00100OUT_FAN[1]
01001OMUX_ES7
01010HEX_S3[5]
01100OUT_FAN[7]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_DCM switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00010OUT_FAN[0]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_DCM switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_DCM switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_DCM switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_E2
01010LV[6]
01100OUT_FAN[4]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_DCM switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX[6]
01010LV[6]
01100OUT_FAN[3]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_SE3
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_E8
01010LV[6]
01100OUT_FAN[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_ES7
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00001OUT_FAN[3]
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_DCM switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
00100OUT_FAN[2]
01001OMUX_NW10
01010LV[6]
01100OUT_FAN[4]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01001OUT_FAN[5]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_DCM switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
00100OUT_FAN[4]
01001OMUX_WN14
01010LV[6]
01100OUT_FAN[3]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
00100OUT_FAN[5]
01001OMUX_NW10
01010HEX_W3[4]
01100OUT_FAN[2]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
00100OUT_FAN[1]
01001OMUX_N12
01010LV[6]
01100OUT_FAN[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_DCM switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
00100OUT_FAN[0]
01001OMUX_WN14
01010HEX_W3[6]
01100OUT_FAN[7]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_DCM switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00001OUT_FAN[6]
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_DCM switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_DCM switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_DCM switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_DCM switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_DCM switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_DCM switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_DCM switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_DCM switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_DCM switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][36]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[4][32]MAIN[4][33]MAIN[4][34]MAIN[4][35]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
000000000000000PULLUP
000010000000001GCLK[0]
000010000000010GCLK[1]
000010000000100GCLK[2]
000010000001000GCLK[3]
000010100000000DBL_E1[4]
000011000000000DBL_E0[4]
000100000000001GCLK[4]
000100000000010GCLK[5]
000100000000100GCLK[6]
000100000001000GCLK[7]
000100100000000DBL_W1[4]
000101000000000DBL_W2[4]
001000000010000DCM_CLKPAD[0]
001000000100000DCM_CLKPAD[1]
001000001000000DCM_CLKPAD[2]
001000010000000DCM_CLKPAD[3]
010000000000001HEX_S3[4]
010000000000010HEX_N3[4]
010000000000100HEX_S2[4]
010000000001000HEX_N4[4]
010000100000000HEX_N5[4]
010001000000000HEX_S1[4]
100000000000001HEX_S6[4]
100000000000010HEX_N0[4]
100000000000100HEX_S5[4]
100000000001000HEX_N1[4]
100000100000000HEX_S4[4]
100001000000000HEX_N2[4]
spartan3 INT_DCM switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[5][27]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[5][31]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
000000000000000PULLUP
000010000000001GCLK[0]
000010000000010GCLK[1]
000010000000100GCLK[2]
000010000001000GCLK[3]
000010100000000DBL_E1[3]
000011000000000DBL_E0[3]
000100000000001GCLK[4]
000100000000010GCLK[5]
000100000000100GCLK[6]
000100000001000GCLK[7]
000100100000000DBL_W1[3]
000101000000000DBL_W2[3]
001000000010000DCM_CLKPAD[0]
001000000100000DCM_CLKPAD[1]
001000001000000DCM_CLKPAD[2]
001000010000000DCM_CLKPAD[3]
010000000000001HEX_S3[4]
010000000000010HEX_N3[4]
010000000000100HEX_S2[4]
010000000001000HEX_N4[4]
010000100000000HEX_N5[4]
010001000000000HEX_S1[4]
100000000000001HEX_S6[4]
100000000000010HEX_N0[4]
100000000000100HEX_S5[4]
100000000001000HEX_N1[4]
100000100000000HEX_S4[4]
100001000000000HEX_N2[4]
spartan3 INT_DCM switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[5][36]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[5][32]MAIN[5][33]MAIN[5][34]MAIN[5][35]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
000000000000000PULLUP
000010000000001GCLK[0]
000010000000010GCLK[1]
000010000000100GCLK[2]
000010000001000GCLK[3]
000010100000000DBL_E1[4]
000011000000000DBL_E0[4]
000100000000001GCLK[4]
000100000000010GCLK[5]
000100000000100GCLK[6]
000100000001000GCLK[7]
000100100000000DBL_W1[4]
000101000000000DBL_W2[4]
001000000010000DCM_CLKPAD[0]
001000000100000DCM_CLKPAD[1]
001000001000000DCM_CLKPAD[2]
001000010000000DCM_CLKPAD[3]
010000000000001HEX_S3[4]
010000000000010HEX_N3[4]
010000000000100HEX_S2[4]
010000000001000HEX_N4[4]
010000100000000HEX_N5[4]
010001000000000HEX_S1[4]
100000000000001HEX_S6[4]
100000000000010HEX_N0[4]
100000000000100HEX_S5[4]
100000000001000HEX_N1[4]
100000100000000HEX_S4[4]
100001000000000HEX_N2[4]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000PULLUP
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00010000OUT_FAN[6]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11101000OUT_FAN[1]
11110000DBL_S1[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000PULLUP
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
11101000OUT_FAN[2]
11110000OUT_FAN[5]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000PULLUP
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00100100OUT_FAN[4]
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11101000OUT_FAN[3]
11110000OMUX_N10
spartan3 INT_DCM switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000PULLUP
00000001OMUX[13]
00000010OMUX_SW5
00000100OUT_FAN[7]
00001000IMUX_FAN_BY[2]
00010000OUT_FAN[0]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Switchbox PTE2OMUX

spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[12]
BitsDestination
MAIN[3][23]MAIN[3][22]MAIN[3][21]OUT_SEC[12]
Source
000off
001IMUX_DATA[31]
010IMUX_DATA[23]
011IMUX_CLK_OPTINV[3]
100IMUX_DATA[19]
101IMUX_DATA[3]
110IMUX_DATA[27]
spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[13]
BitsDestination
MAIN[3][16]MAIN[3][18]MAIN[3][17]OUT_SEC[13]
Source
000off
001IMUX_DATA[22]
010IMUX_DATA[30]
011IMUX_CLK_OPTINV[2]
100IMUX_DATA[18]
101IMUX_DATA[26]
spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[14]
BitsDestination
MAIN[3][48]MAIN[3][49]MAIN[3][50]OUT_SEC[14]
Source
000off
001IMUX_DATA[29]
010IMUX_DATA[21]
011IMUX_CLK_OPTINV[1]
100IMUX_DATA[17]
101IMUX_DATA[2]
110IMUX_DATA[25]
spartan3 INT_DCM switchbox PTE2OMUX muxes OUT_SEC[15]
BitsDestination
MAIN[3][42]MAIN[3][41]MAIN[3][40]OUT_SEC[15]
Source
000off
001IMUX_DATA[16]
010IMUX_DATA[20]
011IMUX_DATA[24]
100IMUX_DATA[28]

Bitstream

spartan3 INT_DCM rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - INT: mux OMUX[15] bit 6 INT: mux OMUX[14] bit 5 - INT: mux IMUX_DATA[31] bit 2 - INT: mux IMUX_DATA[23] bit 4 - INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - - - INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[31] bit 6 - - - INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - - - INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_DATA[31] bit 5 - INT: mux IMUX_DATA[31] bit 1 - INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - INT: mux OMUX[14] bit 3 INT: mux OMUX[15] bit 2 INT: mux IMUX_DATA[31] bit 7 - INT: mux IMUX_DATA[23] bit 1 - INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - - - INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 2 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 - INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - - - INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 0 - - - - - INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - - - INT: mux OMUX[14] bit 7 INT: mux OMUX[15] bit 4 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 - - INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - - - INT: mux OMUX[14] bit 6 INT: mux OMUX[14] bit 4 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 - INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - - - INT: mux OMUX[12] bit 6 INT: mux OMUX[12] bit 4 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 - INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - - - INT: mux OMUX[12] bit 7 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 - INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - - - INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 - INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - - - INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 - INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - - - INT: mux OMUX[12] bit 3 INT: mux OMUX[13] bit 2 - INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 - INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - PTE2OMUX: mux OUT_SEC[14] bit 0 - - INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 - - - - - INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - PTE2OMUX: mux OUT_SEC[14] bit 1 - - INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - PTE2OMUX: mux OUT_SEC[14] bit 2 - - INT: mux OMUX[13] bit 6 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[29] bit 7 - INT: mux IMUX_DATA[29] bit 1 - INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 6 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[29] bit 5 - INT: mux IMUX_DATA[29] bit 0 - INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_CLK[3] bit 10 INT: mux IMUX_CLK[3] bit 14 INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[29] bit 3 - INT: mux IMUX_DATA[21] bit 0 - INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_CLK[3] bit 11 INT: mux IMUX_CLK[3] bit 13 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 - - - - - INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 - INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 - INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - PTE2OMUX: mux OUT_SEC[15] bit 2 INT: mux IMUX_CLK[1] bit 9 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_DATA[16] bit 7 - - - INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - PTE2OMUX: mux OUT_SEC[15] bit 1 INT: mux IMUX_CLK[3] bit 8 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[10] bit 7 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 5 - INT: mux IMUX_DATA[16] bit 0 - INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - PTE2OMUX: mux OUT_SEC[15] bit 0 INT: mux IMUX_CLK[1] bit 8 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 6 INT: mux OMUX[10] bit 4 INT: mux IMUX_DATA[16] bit 3 - INT: mux IMUX_DATA[24] bit 0 - INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 11 INT: mux IMUX_CLK[1] bit 14 INT: mux OMUX[8] bit 6 INT: mux OMUX[8] bit 4 - - - - - INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 13 INT: mux OMUX[8] bit 7 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 - INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 10 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 0 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - INT: mux IMUX_CLK[1] bit 12 INT: mux IMUX_CLK[3] bit 12 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[3] bit 4 INT: mux OMUX[8] bit 3 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[3] bit 6 INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[3] bit 7 INT: mux OMUX[9] bit 6 INT: mux OMUX[8] bit 5 INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - INT: mux IMUX_CLK[2] bit 7 INT: mux OMUX[7] bit 6 INT: mux OMUX[6] bit 5 INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux OMUX[6] bit 3 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - INT: mux IMUX_CLK[2] bit 12 INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - - - INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 0 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 - INT: mux OMUX[6] bit 7 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[0] bit 3 - INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - - - INT: mux OMUX[6] bit 6 INT: mux OMUX[6] bit 4 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - PTE2OMUX: mux OUT_SEC[12] bit 2 - - INT: mux OMUX[4] bit 6 INT: mux OMUX[4] bit 4 - INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - PTE2OMUX: mux OUT_SEC[12] bit 1 INT: mux IMUX_CLK[2] bit 8 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[4] bit 7 INT: mux OMUX[5] bit 4 - INT: mux IMUX_DATA[27] bit 6 - INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - PTE2OMUX: mux OUT_SEC[12] bit 0 - INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 0 - INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - - INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 2 - - INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 - INT: mux OMUX[4] bit 3 INT: mux OMUX[5] bit 2 - - INT: mux IMUX_DATA[30] bit 2 - INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - PTE2OMUX: mux OUT_SEC[13] bit 1 INT: mux IMUX_CLK[2] bit 11 INT: mux IMUX_CLK[2] bit 13 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - PTE2OMUX: mux OUT_SEC[13] bit 0 INT: mux IMUX_CLK[2] bit 10 INT: mux IMUX_CLK[2] bit 14 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 5 - INT: mux IMUX_DATA[22] bit 7 - INT: mux IMUX_DATA[30] bit 7 - INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - PTE2OMUX: mux OUT_SEC[13] bit 2 - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 6 INT: mux OMUX[4] bit 5 - INT: mux IMUX_DATA[22] bit 6 - INT: mux IMUX_DATA[30] bit 6 - INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 6 INT: mux OMUX[2] bit 5 - INT: mux IMUX_DATA[22] bit 5 - INT: mux IMUX_DATA[30] bit 5 - INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 5 - - - - - INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - - - INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - - - INT: mux OMUX[2] bit 3 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[22] bit 4 - INT: mux IMUX_DATA[25] bit 0 - INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - - - INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 2 - INT: mux IMUX_DATA[25] bit 2 - INT: mux IMUX_DATA[17] bit 4 - INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - - - INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 0 - INT: mux IMUX_DATA[25] bit 7 - INT: mux IMUX_DATA[17] bit 7 - INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - - - INT: mux OMUX[2] bit 7 INT: mux OMUX[3] bit 4 - INT: mux IMUX_DATA[25] bit 5 - INT: mux IMUX_DATA[17] bit 5 - INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - - - INT: mux OMUX[2] bit 6 INT: mux OMUX[2] bit 4 - INT: mux IMUX_DATA[25] bit 6 - INT: mux IMUX_DATA[17] bit 6 - INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - - - INT: mux OMUX[0] bit 6 INT: mux OMUX[0] bit 4 INT: mux IMUX_DATA[25] bit 3 - - - INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - - - INT: mux OMUX[0] bit 7 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 - INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - - - INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 0 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - - - INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 2 - - INT: mux IMUX_DATA[20] bit 0 - - INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - - - INT: mux OMUX[0] bit 3 INT: mux OMUX[1] bit 2 - INT: mux IMUX_DATA[20] bit 5 - INT: mux IMUX_DATA[28] bit 5 - INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - - - INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 - INT: mux IMUX_DATA[20] bit 6 - INT: mux IMUX_DATA[28] bit 6 - INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - - - INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 5 - INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 - INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - - - INT: mux OMUX[1] bit 6 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[20] bit 4 - INT: mux IMUX_DATA[28] bit 3 - INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0

INT_DCM_S3_DUMMY

Used for the dummy interconnect tile in DCM holes on Spartan 3 devices with more than 2 BRAM columns. Not associated with any primitive.

Tile INT_DCM_S3_DUMMY

Cells: 1

Switchbox INT

spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[14][22]MAIN[13][20]DBL_W0[2]
Source
000000off
000100HEX_E6[2]
001000HEX_N6[2]
010001OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_W2[0]
100010DBL_S2[4]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_W2[2]
110010DBL_S1[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[14][54]MAIN[13][52]DBL_W0[6]
Source
000000off
000001OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_W2[4]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_W2[6]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[13][60]MAIN[14][62]DBL_W0[7]
Source
000000off
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_W2[5]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_W2[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[15][22]MAIN[13][23]MAIN[13][22]MAIN[13][21]DBL_E0[2]
Source
000000off
000001OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010001DBL_E2[2]
010010DBL_S2[4]
010100DBL_N2[1]
011000HEX_N3[2]
100100HEX_S6[3]
101000HEX_W6[2]
110001DBL_E2[4]
110010DBL_S1[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][2]MAIN[15][3]MAIN[13][0]MAIN[15][1]MAIN[13][1]MAIN[13][2]DBL_S0[0]
Source
000000off
000001OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001DBL_S2[2]
010010DBL_W1[0]
010100DBL_W2_N[6]
011000HEX_E3[0]
100100HEX_W6_N[7]
101000HEX_S6[0]
110001DBL_S2[0]
110010DBL_E1[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][17]MAIN[13][18]DBL_S0[2]
Source
000000off
000100HEX_N6[2]
001000HEX_E6[2]
010001OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_S2[4]
100010DBL_W1[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_S2[2]
110010DBL_E1[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][26]MAIN[15][27]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
001000HEX_N6[3]
010001DBL_S2[5]
010010DBL_W1[3]
010100DBL_E2[4]
011000HEX_W3[3]
100010HEX_S6[3]
101000HEX_W6[2]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][57]MAIN[13][56]MAIN[13][58]DBL_S0[7]
Source
000000off
000001OMUX_WS1
000010HEX_E6[7]
001000HEX_N6[7]
010001OMUX_SE3
010010HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[1]
100010DBL_W1[7]
100100DBL_E2_S[0]
101000HEX_W3[7]
110001DBL_S2[7]
110010DBL_W2[5]
110100DBL_E1[7]
111000HEX_E3[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[14][1]MAIN[13][3]DBL_N0[0]
Source
000000off
000001OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_N2[0]
100010DBL_W1[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_N3[6]
110010DBL_E1[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[14][17]MAIN[13][19]DBL_N0[2]
Source
000000off
000001OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010001OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_N2[2]
100010DBL_W1[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_N2[0]
110010DBL_E1[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][57]MAIN[14][56]MAIN[13][59]DBL_N0[7]
Source
000000off
000001OMUX_N11
000010HEX_E6[7]
001000HEX_N6[7]
010001OMUX_W9
010010HEX_S6[7]
011000HEX_W6[6]
100001DBL_N2[7]
100010DBL_W1[7]
100100DBL_E2_S[0]
101000HEX_W3[7]
110001DBL_N2[5]
110010DBL_W2[5]
110100DBL_E1[7]
111000HEX_E3[7]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
01001OMUX_NW10
01010HEX_N7[7]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00010HEX_N6[0]
01001OMUX_W1
01010HEX_S3[1]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[18][21]MAIN[16][23]MAIN[16][22]HEX_W0[2]
Source
00000off
00010HEX_S6[4]
01001OMUX_WN14
01010HEX_N6[1]
10001HEX_W6[0]
10010LH[6]
10100HEX_N3[2]
11001HEX_W6[2]
11010HEX_S3[2]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
01001OMUX_NW10
01010HEX_S3[3]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
01001OMUX_N12
01010HEX_N6[3]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
01001OMUX_WN14
01010HEX_S3[5]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[18][53]MAIN[16][55]MAIN[16][54]HEX_W0[6]
Source
00000off
00001OMUX_SW5
00010HEX_S7[0]
01001OMUX_W9
01010HEX_N6[5]
10001HEX_W6[4]
10010LH[6]
10100HEX_N3[6]
11001HEX_W6[6]
11010HEX_S3[6]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[18][60]MAIN[17][63]HEX_W0[7]
Source
00000off
00010OMUX_WS1
00100HEX_N6[6]
01001OMUX_S0
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_W6[5]
10100LH[0]
11001LH[12]
11010HEX_W6[7]
11100HEX_S7[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
01001OMUX_E2
01010HEX_N7[7]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
01001OMUX_S4
01010HEX_S3[1]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][21]MAIN[16][20]MAIN[17][23]MAIN[17][22]MAIN[18][20]HEX_E0[2]
Source
00000off
00001OMUX_NE12
00010HEX_S6[4]
01001HEX_E6[2]
01010LH[6]
01100HEX_N3[2]
10010HEX_N6[1]
11001HEX_E6[4]
11010HEX_S3[2]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
01001OMUX_SE3
01010HEX_S3[3]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
01001OMUX_E8
01010HEX_N6[3]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
01001OMUX_ES7
01010HEX_S3[5]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][55]MAIN[17][54]MAIN[18][52]HEX_E0[6]
Source
00000off
00010HEX_S7[0]
01001OMUX_SE3
01010HEX_N6[5]
10001HEX_E6[6]
10010LH[6]
10100HEX_N3[6]
11001HEX_E6_S[0]
11010HEX_S3[6]
11100LH[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][0]MAIN[17][1]MAIN[18][3]HEX_S0[0]
Source
00000off
00001OMUX_S0
00010HEX_W6_N[6]
01010HEX_W3[0]
10001HEX_S6[2]
10010HEX_E6[1]
10100LV[0]
11001HEX_S6[0]
11010HEX_E3[0]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00010HEX_E6[2]
01001OMUX_E2
01010LV[6]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][16]MAIN[17][17]MAIN[18][19]HEX_S0[2]
Source
00000off
00010HEX_W6[0]
01001OMUX_S4
01010HEX_W3[2]
10001HEX_S6[4]
10010HEX_E6[3]
10100LV[0]
11001HEX_S6[2]
11010HEX_E3[2]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][26]MAIN[17][27]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
01001HEX_S6[5]
01010HEX_W3[3]
01100HEX_W6[1]
10010LV[6]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
01001OMUX_SE3
01010HEX_W3[4]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
01001OMUX_E8
01010LV[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
01001OMUX_ES7
01010HEX_W3[6]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[18][58]MAIN[16][56]MAIN[16][57]HEX_S0[7]
Source
00000off
00001OMUX_WS1
00010HEX_E6_S[0]
01001OMUX_SE3
01010LV[6]
10001HEX_S7[1]
10010HEX_W3[7]
10100HEX_W6[5]
11001HEX_S6[7]
11010HEX_E3[7]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[18][2]MAIN[16][0]MAIN[16][1]HEX_N0[0]
Source
00000off
00001OMUX_EN8
00010HEX_W6_N[6]
01001OMUX_N9
01010HEX_W3[0]
10001HEX_N6[0]
10010HEX_E6[1]
10100LV[0]
11001HEX_N7[6]
11010HEX_E3[0]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
01001OMUX_NW10
01010LV[6]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[18][18]MAIN[16][16]MAIN[16][17]HEX_N0[2]
Source
00000off
00001OMUX_NE12
00010HEX_W6[0]
01001OMUX_W1
01010HEX_W3[2]
10001HEX_N6[2]
10010HEX_E6[3]
10100LV[0]
11001HEX_N6[0]
11010HEX_E3[2]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
01001OMUX_WN14
01010LV[6]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
01001OMUX_NW10
01010HEX_W3[4]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
01001OMUX_N12
01010LV[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00010HEX_W6[4]
01001OMUX_WN14
01010HEX_W3[6]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][56]MAIN[17][57]MAIN[18][59]HEX_N0[7]
Source
00000off
00001OMUX_N11
00010HEX_E6_S[0]
01001OMUX_W9
01010LV[6]
10001HEX_N6[7]
10010HEX_W3[7]
10100HEX_W6[5]
11001HEX_N6[5]
11010HEX_E3[7]
11100LV[18]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][41]MAIN[18][40]LH[0]
Source
000off
001DBL_W1[4]
010DBL_E1[4]
101OMUX_S4
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][32]MAIN[18][33]LH[12]
Source
000off
001DBL_W1[4]
010DBL_E1[4]
101OMUX_S4
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][0]MAIN[18][1]MAIN[18][6]LV[0]
Source
00000off
00001OMUX_E2
00010HEX_E6[0]
00100HEX_E5[0]
01001DBL_E1[2]
01010HEX_E2[0]
10100HEX_E1[0]
11001HEX_E3[0]
11010DBL_W1[1]
11100HEX_E4[0]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][57]MAIN[18][63]LV[6]
Source
00000off
00001OMUX_W9
00010DBL_W1[7]
00100HEX_W1[6]
01001DBL_E1[7]
01010HEX_W3[6]
01100HEX_W0[6]
10001HEX_W2[6]
11001HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][17]MAIN[18][16]MAIN[18][15]LV[12]
Source
00000off
00001OMUX_E2
00010HEX_E6[0]
00100HEX_E5[0]
01001DBL_E1[2]
01010HEX_E2[0]
10100HEX_E1[0]
11001HEX_E3[0]
11010DBL_W1[1]
11100HEX_E4[0]
spartan3 INT_DCM_S3_DUMMY switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][48]MAIN[18][46]LV[18]
Source
00000off
00001OMUX_W9
00010DBL_W1[7]
00100HEX_W1[6]
01001DBL_E1[7]
01010HEX_W3[6]
01100HEX_W0[6]
10001HEX_W2[6]
11001HEX_W4[6]
11100HEX_W5[6]

Bitstream

spartan3 INT_DCM_S3_DUMMY rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - - - - - - - - INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 0 INT: mux LV[6] bit 0
B62 - - - - - - - - - - - - - INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - - - - - - - - - - INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - - - - - - - - INT: mux DBL_W0[7] bit 1 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 1
B59 - - - - - - - - - - - - - INT: mux DBL_N0[7] bit 0 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 0
B58 - - - - - - - - - - - - - INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 2
B57 - - - - - - - - - - - - - INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_N0[7] bit 1 INT: mux LV[6] bit 1
B56 - - - - - - - - - - - - - INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 3
B55 - - - - - - - - - - - - - INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[6] bit 4
B54 - - - - - - - - - - - - - INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 1 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 0 INT: mux HEX_E0[6] bit 1 INT: mux LV[18] bit 4
B53 - - - - - - - - - - - - - INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 2
B52 - - - - - - - - - - - - - INT: mux DBL_W0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - - - - - - - - - - INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - - - - - - - - - - - INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - - - - - - - - - - - INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - - - - - - - - - - - INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 1
B47 - - - - - - - - - - - - - INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - - - - - - - - - - INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 0
B45 - - - - - - - - - - - - - INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - - - - - - - - - - INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - - - - - - - - - - INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - - - - - - - - - - - INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - - - - - - - - - - - INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 1
B40 - - - - - - - - - - - - - INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 0
B39 - - - - - - - - - - - - - INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - - - - - - - - - - INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - - - - - - - - - - INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - - - - - - - - INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - - - - - - - - INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - - - - - - - - INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - - - - - - - - INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 0
B32 - - - - - - - - - - - - - INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 1
B31 - - - - - - - - - - - - - INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - - - - - - - - INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - - - - - - - - INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - - - - - - - - INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - - - - - - - - INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 3 INT: mux HEX_N0[3] bit 0
B26 - - - - - - - - - - - - - INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 4 INT: mux HEX_S0[3] bit 2
B25 - - - - - - - - - - - - - INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - - - - - - - - - - INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - - - - - - - - - - - INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 0
B22 - - - - - - - - - - - - - INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 0 INT: mux HEX_E0[2] bit 1 INT: mux LH[6] bit 1
B21 - - - - - - - - - - - - - INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 2
B20 - - - - - - - - - - - - - INT: mux DBL_W0[2] bit 0 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 0
B19 - - - - - - - - - - - - - INT: mux DBL_N0[2] bit 0 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 0
B18 - - - - - - - - - - - - - INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 2
B17 - - - - - - - - - - - - - INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 0 INT: mux HEX_S0[2] bit 1 INT: mux LV[12] bit 2
B16 - - - - - - - - - - - - - INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 1
B15 - - - - - - - - - - - - - INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 0
B14 - - - - - - - - - - - - - INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - - - - - - - - - - INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - - - - - - - - - - INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - - - - - - - - - - INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - - - - - - - - - - INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - - - - - - - - - - INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - - - - - - - - - - INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - - - - - - - - - - INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - - - - - - - - - - INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 0
B5 - - - - - - - - - - - - - INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - - - - - - - - - - INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - - - - - - - - - - INT: mux DBL_N0[0] bit 0 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 0
B2 - - - - - - - - - - - - - INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 2
B1 - - - - - - - - - - - - - INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 1 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 0 INT: mux HEX_S0[0] bit 1 INT: mux LV[0] bit 1
B0 - - - - - - - - - - - - - INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2

INT_DCM_S3E_DUMMY

Used for the dummy interconnect tile in DCM holes on Spartan 3E devices with 2 DCMs. Not associated with any primitive.

Tile INT_DCM_S3E_DUMMY

Cells: 1

Switchbox INT

spartan3 INT_DCM_S3E_DUMMY switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[5][37]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[5][16]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[5][47]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[0]
BitsDestination
MAIN[7][7]MAIN[6][5]MAIN[6][3]MAIN[7][4]MAIN[6][7]MAIN[6][6]OMUX[0]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[1]
BitsDestination
MAIN[7][6]MAIN[7][5]MAIN[6][4]MAIN[7][3]MAIN[6][1]MAIN[6][0]OMUX[1]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[2]
BitsDestination
MAIN[7][8]MAIN[6][10]MAIN[6][12]MAIN[7][11]MAIN[6][9]MAIN[6][8]OMUX[2]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[3]
BitsDestination
MAIN[7][9]MAIN[7][10]MAIN[6][11]MAIN[7][12]MAIN[6][15]MAIN[6][14]OMUX[3]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[4]
BitsDestination
MAIN[7][23]MAIN[6][21]MAIN[6][19]MAIN[7][20]MAIN[6][23]MAIN[6][22]OMUX[4]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[5]
BitsDestination
MAIN[7][22]MAIN[7][21]MAIN[6][20]MAIN[7][19]MAIN[6][17]MAIN[6][16]OMUX[5]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[6]
BitsDestination
MAIN[7][24]MAIN[6][26]MAIN[6][28]MAIN[7][27]MAIN[6][25]MAIN[6][24]OMUX[6]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[7]
BitsDestination
MAIN[7][25]MAIN[7][26]MAIN[6][27]MAIN[7][28]MAIN[6][31]MAIN[6][30]OMUX[7]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[8]
BitsDestination
MAIN[7][39]MAIN[6][37]MAIN[6][35]MAIN[7][36]MAIN[6][39]MAIN[6][38]OMUX[8]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[9]
BitsDestination
MAIN[7][38]MAIN[7][37]MAIN[6][36]MAIN[7][35]MAIN[6][33]MAIN[6][32]OMUX[9]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[10]
BitsDestination
MAIN[7][40]MAIN[6][42]MAIN[6][44]MAIN[7][43]MAIN[6][41]MAIN[6][40]OMUX[10]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[11]
BitsDestination
MAIN[7][41]MAIN[7][42]MAIN[6][43]MAIN[7][44]MAIN[6][47]MAIN[6][46]OMUX[11]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[12]
BitsDestination
MAIN[7][55]MAIN[6][53]MAIN[6][51]MAIN[7][52]MAIN[6][55]MAIN[6][54]OMUX[12]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[13]
BitsDestination
MAIN[7][54]MAIN[7][53]MAIN[6][52]MAIN[7][51]MAIN[6][49]MAIN[6][48]OMUX[13]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[14]
BitsDestination
MAIN[7][56]MAIN[6][58]MAIN[6][60]MAIN[7][59]MAIN[6][57]MAIN[6][56]OMUX[14]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes OMUX[15]
BitsDestination
MAIN[7][57]MAIN[7][58]MAIN[6][59]MAIN[7][60]MAIN[6][63]MAIN[6][62]OMUX[15]
Source
000000off
000111OUT_SEC[12]
001011OUT_SEC[13]
010011OUT_SEC[14]
100011OUT_SEC[15]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[14][4]MAIN[14][5]MAIN[15][7]MAIN[14][7]MAIN[14][6]MAIN[13][4]DBL_W0[0]
Source
000000off
000001OMUX_S0
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_NW10
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_W2_N[6]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_W2[0]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[14][12]MAIN[14][13]MAIN[14][14]MAIN[15][15]MAIN[14][15]MAIN[13][12]DBL_W0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_W1
010010HEX_S6[2]
010100HEX_W6[1]
100001DBL_W2_N[7]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_W2[1]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[14][20]MAIN[14][21]MAIN[15][23]MAIN[14][23]MAIN[13][20]MAIN[14][22]DBL_W0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX_WN14
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_W2[0]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_W2[2]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[14][28]MAIN[14][29]MAIN[14][30]MAIN[15][31]MAIN[14][31]MAIN[13][28]DBL_W0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
000100HEX_N6[3]
010001OMUX_NW10
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_W2[1]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_W2[3]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[14][36]MAIN[14][37]MAIN[15][39]MAIN[14][39]MAIN[14][38]MAIN[13][36]DBL_W0[4]
Source
000000off
000001OMUX_WS1
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_N12
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_W2[2]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_W2[4]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[14][44]MAIN[14][45]MAIN[14][46]MAIN[15][47]MAIN[14][47]MAIN[13][44]DBL_W0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
000100HEX_N6[5]
010001OMUX_WN14
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_W2[3]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_W2[5]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[14][52]MAIN[14][53]MAIN[15][55]MAIN[14][55]MAIN[13][52]MAIN[14][54]DBL_W0[6]
Source
000000off
000010OMUX_SW5
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_S3[0]
100010DBL_W2[4]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_S1[6]
110010DBL_W2[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[14][60]MAIN[14][61]MAIN[15][63]MAIN[14][63]MAIN[14][62]MAIN[13][60]DBL_W0[7]
Source
000000off
000001OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[9]
010010OMUX_S0
010100HEX_S7[0]
011000HEX_W6[7]
100001DBL_W2[5]
100010HEX_N3[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001DBL_W2[7]
110010HEX_S3[7]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[15][4]MAIN[15][5]MAIN[15][6]MAIN[13][7]MAIN[13][6]MAIN[13][5]DBL_E0[0]
Source
000000off
000001OMUX_EN8
000100HEX_E6[0]
001000HEX_N6[0]
010001OMUX_E2
010100HEX_S6[1]
011000HEX_W6[0]
100001DBL_E2[0]
100010DBL_S2[2]
100100DBL_N3[7]
101000HEX_N3[0]
110001DBL_E2[2]
110010DBL_S1[0]
110100DBL_N1[0]
111000HEX_S3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[15][12]MAIN[15][13]MAIN[13][14]MAIN[15][14]MAIN[13][15]MAIN[13][13]DBL_E0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
000100HEX_N6[1]
010001OMUX_S4
010010HEX_S6[2]
010100HEX_W6[1]
100001DBL_E2[1]
100010DBL_S1[1]
100100DBL_N2[0]
101000HEX_N3[1]
110001DBL_E2[3]
110010DBL_S2[3]
110100DBL_N1[1]
111000HEX_S3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][20]MAIN[15][21]MAIN[15][22]MAIN[13][23]MAIN[13][21]MAIN[13][22]DBL_E0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_E6[2]
001000HEX_N6[2]
010010OMUX[6]
010100HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[4]
100010DBL_E2[2]
100100DBL_N2[1]
101000HEX_N3[2]
110001DBL_S1[2]
110010DBL_E2[4]
110100DBL_N1[2]
111000HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[15][28]MAIN[15][29]MAIN[13][30]MAIN[15][30]MAIN[13][31]MAIN[13][29]DBL_E0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
000100HEX_N6[3]
010001OMUX_SE3
010010HEX_S6[4]
010100HEX_W6[3]
100001DBL_E2[3]
100010DBL_S1[3]
100100DBL_N2[2]
101000HEX_N3[3]
110001DBL_E2[5]
110010DBL_S2[5]
110100DBL_N1[3]
111000HEX_S3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[15][36]MAIN[15][37]MAIN[15][38]MAIN[13][39]MAIN[13][38]MAIN[13][37]DBL_E0[4]
Source
000000off
000001OMUX_E7
000100HEX_E6[4]
001000HEX_N6[4]
010001OMUX_E8
010100HEX_S6[5]
011000HEX_W6[4]
100001DBL_E2[4]
100010DBL_S2[6]
100100DBL_N2[3]
101000HEX_N3[4]
110001DBL_E2[6]
110010DBL_S1[4]
110100DBL_N1[4]
111000HEX_S3[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[15][44]MAIN[15][45]MAIN[13][46]MAIN[15][46]MAIN[13][47]MAIN[13][45]DBL_E0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
000100HEX_N6[5]
010001OMUX_ES7
010010HEX_S6[6]
010100HEX_W6[5]
100001DBL_E2[5]
100010DBL_S1[5]
100100DBL_N2[4]
101000HEX_N3[5]
110001DBL_E2[7]
110010DBL_S2[7]
110100DBL_N1[5]
111000HEX_S3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[15][52]MAIN[15][53]MAIN[15][54]MAIN[13][55]MAIN[13][54]MAIN[13][53]DBL_E0[6]
Source
000000off
000001OMUX[9]
000100HEX_E6[6]
001000HEX_N6[6]
010001OMUX_SE3
010010OMUX[11]
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2[6]
100010DBL_S3[0]
100100DBL_N2[5]
101000HEX_N3[6]
110001DBL_E2_S[0]
110010DBL_S1[6]
110100DBL_N1[6]
111000HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[15][60]MAIN[15][61]MAIN[15][62]MAIN[13][63]MAIN[13][61]MAIN[13][62]DBL_E0[7]
Source
000000off
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX_S0
010010OMUX_S2
010100HEX_S7[0]
011000HEX_W6[7]
100001HEX_N3[7]
100010DBL_E2[7]
100100DBL_S1[7]
101000DBL_N2[6]
110001HEX_S3[7]
110010DBL_E2_S[1]
110100DBL_S3[1]
111000DBL_N1[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][3]MAIN[15][2]MAIN[13][0]MAIN[15][1]MAIN[13][2]MAIN[13][1]DBL_S0[0]
Source
000000off
000010OMUX_S0
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX[2]
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_S2[2]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_S2[0]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[15][11]MAIN[15][10]MAIN[15][9]MAIN[13][9]MAIN[13][8]MAIN[13][10]DBL_S0[1]
Source
000000off
000001OMUX[2]
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_E2
010010HEX_S6[1]
011000HEX_W6[0]
100001DBL_S2[3]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_S2[1]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][19]MAIN[15][18]MAIN[13][16]MAIN[15][17]MAIN[13][18]MAIN[13][17]DBL_S0[2]
Source
000000off
000001OMUX[4]
000010OMUX[6]
000100HEX_N6[2]
001000HEX_E6[2]
010010OMUX_S4
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_S2[4]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_S2[2]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[15][27]MAIN[15][26]MAIN[15][25]MAIN[13][25]MAIN[13][24]MAIN[13][26]DBL_S0[3]
Source
000000off
000001OMUX_W6
000010HEX_E6[3]
001000HEX_N6[3]
010001OMUX[6]
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_S2[5]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_S2[3]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[15][35]MAIN[15][34]MAIN[13][32]MAIN[15][33]MAIN[13][33]MAIN[13][34]DBL_S0[4]
Source
000000off
000001OMUX_WS1
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_SE3
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_S2[6]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_S2[4]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[15][43]MAIN[15][42]MAIN[15][41]MAIN[13][41]MAIN[13][40]MAIN[13][42]DBL_S0[5]
Source
000000off
000001OMUX_S3
000010HEX_E6[5]
001000HEX_N6[5]
010001OMUX_E8
010010HEX_S6[5]
011000HEX_W6[4]
100001DBL_S2[7]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_S2[5]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[15][51]MAIN[15][50]MAIN[13][48]MAIN[15][49]MAIN[13][49]MAIN[13][50]DBL_S0[6]
Source
000000off
000001OMUX_SW5
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_ES7
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_S3[0]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_S2[6]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][59]MAIN[15][58]MAIN[15][57]MAIN[13][56]MAIN[13][58]MAIN[13][57]DBL_S0[7]
Source
000000off
000010OMUX_WS1
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_SE3
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_S3[1]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_S2[7]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][3]MAIN[14][2]MAIN[14][0]MAIN[15][0]MAIN[13][3]MAIN[14][1]DBL_N0[0]
Source
000000off
000010OMUX_EN8
000100HEX_N6[0]
001000HEX_E6[0]
010001OMUX[0]
010010OMUX_N9
010100HEX_W6_N[7]
011000HEX_S6[0]
100001DBL_W1[0]
100010DBL_N2[0]
100100DBL_W2_N[6]
101000HEX_E3[0]
110001DBL_E1[0]
110010DBL_N3[6]
110100HEX_W3[0]
111000DBL_E2[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[14][11]MAIN[14][10]MAIN[15][8]MAIN[14][9]MAIN[14][8]MAIN[13][11]DBL_N0[1]
Source
000000off
000001OMUX_N10
000010HEX_E6[1]
001000HEX_N6[1]
010001OMUX_NW10
010010HEX_S6[1]
011000HEX_W6[0]
100001DBL_N2[1]
100010DBL_W1[1]
100100DBL_E2[2]
101000HEX_W3[1]
110001DBL_N3[7]
110010DBL_W2_N[7]
110100DBL_E1[1]
111000HEX_E3[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][19]MAIN[14][18]MAIN[14][16]MAIN[15][16]MAIN[13][19]MAIN[14][17]DBL_N0[2]
Source
000000off
000001OMUX[4]
000010OMUX_NE12
000100HEX_N6[2]
001000HEX_E6[2]
010010OMUX_W1
010100HEX_W6[1]
011000HEX_S6[2]
100001DBL_W1[2]
100010DBL_N2[2]
100100DBL_W2[0]
101000HEX_E3[2]
110001DBL_E1[2]
110010DBL_N2[0]
110100HEX_W3[2]
111000DBL_E2[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[14][27]MAIN[14][26]MAIN[15][24]MAIN[14][25]MAIN[14][24]MAIN[13][27]DBL_N0[3]
Source
000000off
000001OMUX_EN8
000010HEX_E6[3]
001000HEX_N6[3]
010001OMUX_WN14
010010HEX_S6[3]
011000HEX_W6[2]
100001DBL_N2[3]
100010DBL_W1[3]
100100DBL_E2[4]
101000HEX_W3[3]
110001DBL_N2[1]
110010DBL_W2[1]
110100DBL_E1[3]
111000HEX_E3[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[14][35]MAIN[14][34]MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[13][35]DBL_N0[4]
Source
000000off
000001OMUX_E7
000100HEX_N6[4]
001000HEX_E6[4]
010001OMUX_NW10
010100HEX_W6[3]
011000HEX_S6[4]
100001DBL_N2[4]
100010DBL_W1[4]
100100DBL_W2[2]
101000HEX_E3[4]
110001DBL_N2[2]
110010DBL_E1[4]
110100HEX_W3[4]
111000DBL_E2[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[14][43]MAIN[14][42]MAIN[15][40]MAIN[14][41]MAIN[14][40]MAIN[13][43]DBL_N0[5]
Source
000000off
000001OMUX_NE12
000010HEX_E6[5]
001000HEX_N6[5]
010001OMUX_N12
010010HEX_S6[5]
011000HEX_W6[4]
100001DBL_N2[5]
100010DBL_W1[5]
100100DBL_E2[6]
101000HEX_W3[5]
110001DBL_N2[3]
110010DBL_W2[3]
110100DBL_E1[5]
111000HEX_E3[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[14][51]MAIN[14][50]MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[13][51]DBL_N0[6]
Source
000000off
000001OMUX[9]
000100HEX_N6[6]
001000HEX_E6[6]
010001OMUX_WN14
010100HEX_W6[5]
011000HEX_S6[6]
100001DBL_N2[6]
100010DBL_W1[6]
100100DBL_W2[4]
101000HEX_E3[6]
110001DBL_N2[4]
110010DBL_E1[6]
110100HEX_W3[6]
111000DBL_E2[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][59]MAIN[14][58]MAIN[15][56]MAIN[14][56]MAIN[13][59]MAIN[14][57]DBL_N0[7]
Source
000000off
000010OMUX_N11
000100HEX_E6[7]
001000HEX_N6[7]
010001OMUX[11]
010010OMUX_W9
010100HEX_S6[7]
011000HEX_W6[6]
100001DBL_E2_S[0]
100010DBL_N2[7]
100100DBL_W1[7]
101000HEX_W3[7]
110001DBL_E1[7]
110010DBL_N2[5]
110100DBL_W2[5]
111000HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[17][4]MAIN[17][5]MAIN[18][5]MAIN[16][7]MAIN[16][6]HEX_W0[0]
Source
00000off
00001OMUX_S0
00010HEX_S6[2]
01001OMUX_NW10
01010HEX_N7[7]
10001HEX_W6_N[6]
10010LH[6]
10100HEX_N3[0]
11001HEX_W6[0]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[16][12]MAIN[16][13]MAIN[17][15]MAIN[17][14]MAIN[18][12]HEX_W0[1]
Source
00000off
00001OMUX[2]
00010HEX_N6[0]
01001OMUX_W1
01010HEX_S3[1]
10001HEX_W6_N[7]
10010LH[0]
10100HEX_N3[1]
11001HEX_W6[1]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[17][20]MAIN[17][21]MAIN[16][23]MAIN[16][22]MAIN[18][21]HEX_W0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_S6[4]
01010OMUX_WN14
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_W6[0]
10100LH[6]
11001LH[18]
11010HEX_W6[2]
11100HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[16][28]MAIN[16][29]MAIN[17][31]MAIN[17][30]MAIN[18][28]HEX_W0[3]
Source
00000off
00001OMUX_W6
00010HEX_N6[2]
01001OMUX_NW10
01010HEX_S3[3]
10001HEX_W6[1]
10010LH[0]
10100HEX_N3[3]
11001HEX_W6[3]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[17][36]MAIN[17][37]MAIN[18][37]MAIN[16][39]MAIN[16][38]HEX_W0[4]
Source
00000off
00001OMUX_WS1
00010HEX_S6[6]
01001OMUX_N12
01010HEX_N6[3]
10001HEX_W6[2]
10010LH[6]
10100HEX_N3[4]
11001HEX_W6[4]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[16][44]MAIN[16][45]MAIN[17][47]MAIN[17][46]MAIN[18][44]HEX_W0[5]
Source
00000off
00001OMUX_S3
00010HEX_N6[4]
01001OMUX_WN14
01010HEX_S3[5]
10001HEX_W6[3]
10010LH[0]
10100HEX_N3[5]
11001HEX_W6[5]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[17][52]MAIN[17][53]MAIN[16][55]MAIN[16][54]MAIN[18][53]HEX_W0[6]
Source
00000off
00010OMUX_SW5
00100HEX_S7[0]
01001OMUX[11]
01010OMUX_W9
01100HEX_N6[5]
10001HEX_N3[6]
10010HEX_W6[4]
10100LH[6]
11001LH[18]
11010HEX_W6[6]
11100HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[16][60]MAIN[16][61]MAIN[17][62]MAIN[17][63]MAIN[18][60]HEX_W0[7]
Source
00000off
00001OMUX_WS1
00100HEX_N6[6]
01001OMUX[9]
01010OMUX_S0
01100HEX_S3[7]
10001HEX_W6[5]
10010HEX_N3[7]
10100LH[0]
11001HEX_W6[7]
11010LH[12]
11100HEX_S7[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[16][4]MAIN[16][5]MAIN[17][7]MAIN[17][6]MAIN[18][4]HEX_E0[0]
Source
00000off
00001OMUX_EN8
00010HEX_S6[2]
01001OMUX_E2
01010HEX_N7[7]
10001HEX_E6[0]
10010LH[6]
10100HEX_N3[0]
11001HEX_E6[2]
11010HEX_S3[0]
11100LH[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[17][12]MAIN[17][13]MAIN[18][13]MAIN[16][15]MAIN[16][14]HEX_E0[1]
Source
00000off
00001OMUX_N10
00010HEX_N6[0]
01001OMUX_S4
01010HEX_S3[1]
10001HEX_E6[1]
10010LH[0]
10100HEX_N3[1]
11001HEX_E6[3]
11010HEX_S6[3]
11100LH[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[16][20]MAIN[16][21]MAIN[17][22]MAIN[18][20]MAIN[17][23]HEX_E0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_S6[4]
01010OMUX[6]
01100HEX_N6[1]
10001HEX_N3[2]
10010HEX_E6[2]
10100LH[6]
11001LH[18]
11010HEX_E6[4]
11100HEX_S3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[17][28]MAIN[17][29]MAIN[18][29]MAIN[16][31]MAIN[16][30]HEX_E0[3]
Source
00000off
00001OMUX_EN8
00010HEX_N6[2]
01001OMUX_SE3
01010HEX_S3[3]
10001HEX_E6[3]
10010LH[0]
10100HEX_N3[3]
11001HEX_E6[5]
11010HEX_S6[5]
11100LH[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[16][36]MAIN[16][37]MAIN[17][39]MAIN[17][38]MAIN[18][36]HEX_E0[4]
Source
00000off
00001OMUX_E7
00010HEX_S6[6]
01001OMUX_E8
01010HEX_N6[3]
10001HEX_E6[4]
10010LH[6]
10100HEX_N3[4]
11001HEX_E6[6]
11010HEX_S3[4]
11100LH[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[17][44]MAIN[17][45]MAIN[18][45]MAIN[16][47]MAIN[16][46]HEX_E0[5]
Source
00000off
00001OMUX_NE12
00010HEX_N6[4]
01001OMUX_ES7
01010HEX_S3[5]
10001HEX_E6[5]
10010LH[0]
10100HEX_N3[5]
11001HEX_E6[7]
11010HEX_S6[7]
11100LH[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[16][52]MAIN[16][53]MAIN[17][54]MAIN[17][55]MAIN[18][52]HEX_E0[6]
Source
00000off
00001OMUX[9]
00100HEX_S7[0]
01001OMUX_SE3
01010OMUX[11]
01100HEX_N6[5]
10001HEX_E6[6]
10010HEX_N3[6]
10100LH[6]
11001HEX_E6_S[0]
11010LH[18]
11100HEX_S3[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[17][60]MAIN[17][61]MAIN[16][63]MAIN[16][62]MAIN[18][61]HEX_E0[7]
Source
00000off
00010OMUX_N11
00100HEX_N6[6]
01001OMUX_S0
01010OMUX_S2
01100HEX_S3[7]
10001HEX_N3[7]
10010HEX_E6[7]
10100LH[0]
11001LH[12]
11010HEX_E6_S[1]
11100HEX_S7[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[16][3]MAIN[16][2]MAIN[17][1]MAIN[18][3]MAIN[17][0]HEX_S0[0]
Source
00000off
00010OMUX_S0
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX[2]
01100HEX_W3[0]
10001LV[0]
10010HEX_S6[2]
10100HEX_E6[1]
11001LV[12]
11010HEX_S6[0]
11100HEX_E3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][10]MAIN[18][10]MAIN[16][8]MAIN[16][9]HEX_S0[1]
Source
00000off
00001OMUX[2]
00010HEX_E6[2]
01001OMUX_E2
01010LV[6]
10001HEX_S6[3]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_S6[1]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[16][19]MAIN[16][18]MAIN[17][17]MAIN[18][19]MAIN[17][16]HEX_S0[2]
Source
00000off
00001OMUX[4]
00010OMUX[6]
00100HEX_W6[0]
01010OMUX_S4
01100HEX_W3[2]
10001LV[0]
10010HEX_S6[4]
10100HEX_E6[3]
11001LV[12]
11010HEX_S6[2]
11100HEX_E3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][26]MAIN[18][26]MAIN[16][24]MAIN[16][25]HEX_S0[3]
Source
00000off
00001OMUX_W6
00010HEX_E6[4]
01001OMUX[6]
01010LV[6]
10001HEX_S6[5]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_S6[3]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[16][35]MAIN[16][34]MAIN[17][32]MAIN[17][33]MAIN[18][35]HEX_S0[4]
Source
00000off
00001OMUX_WS1
00010HEX_W6[2]
01001OMUX_SE3
01010HEX_W3[4]
10001HEX_S6[6]
10010HEX_E6[5]
10100LV[0]
11001HEX_S6[4]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][42]MAIN[18][42]MAIN[16][40]MAIN[16][41]HEX_S0[5]
Source
00000off
00001OMUX_S3
00010HEX_E6[6]
01001OMUX_E8
01010LV[6]
10001HEX_S6[7]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_S6[5]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[16][51]MAIN[16][50]MAIN[17][48]MAIN[17][49]MAIN[18][51]HEX_S0[6]
Source
00000off
00001OMUX_SW5
00010HEX_W6[4]
01001OMUX_ES7
01010HEX_W3[6]
10001HEX_S7[0]
10010HEX_E6[7]
10100LV[0]
11001HEX_S6[6]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[17][59]MAIN[17][58]MAIN[16][56]MAIN[16][57]MAIN[18][58]HEX_S0[7]
Source
00000off
00010OMUX_WS1
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_SE3
01100LV[6]
10001HEX_W6[5]
10010HEX_S7[1]
10100HEX_W3[7]
11001LV[18]
11010HEX_S6[7]
11100HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[17][3]MAIN[17][2]MAIN[16][0]MAIN[16][1]MAIN[18][2]HEX_N0[0]
Source
00000off
00010OMUX_EN8
00100HEX_W6_N[6]
01001OMUX[0]
01010OMUX_N9
01100HEX_W3[0]
10001LV[0]
10010HEX_N6[0]
10100HEX_E6[1]
11001LV[12]
11010HEX_N7[6]
11100HEX_E3[0]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[16][11]MAIN[16][10]MAIN[17][8]MAIN[17][9]MAIN[18][11]HEX_N0[1]
Source
00000off
00001OMUX_N10
00010HEX_E6[2]
01001OMUX_NW10
01010LV[6]
10001HEX_N6[1]
10010HEX_W3[1]
10100HEX_W6_N[7]
11001HEX_N7[7]
11010HEX_E3[1]
11100LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[17][19]MAIN[17][18]MAIN[16][16]MAIN[16][17]MAIN[18][18]HEX_N0[2]
Source
00000off
00001OMUX[4]
00010OMUX_NE12
00100HEX_W6[0]
01010OMUX_W1
01100HEX_W3[2]
10001LV[0]
10010HEX_N6[2]
10100HEX_E6[3]
11001LV[12]
11010HEX_N6[0]
11100HEX_E3[2]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[16][27]MAIN[16][26]MAIN[17][24]MAIN[17][25]MAIN[18][27]HEX_N0[3]
Source
00000off
00001OMUX_EN8
00010HEX_E6[4]
01001OMUX_WN14
01010LV[6]
10001HEX_N6[3]
10010HEX_W3[3]
10100HEX_W6[1]
11001HEX_N6[1]
11010HEX_E3[3]
11100LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[17][35]MAIN[17][34]MAIN[18][34]MAIN[16][32]MAIN[16][33]HEX_N0[4]
Source
00000off
00001OMUX_E7
00010HEX_W6[2]
01001OMUX_NW10
01010HEX_W3[4]
10001HEX_N6[4]
10010HEX_E6[5]
10100LV[0]
11001HEX_N6[2]
11010HEX_E3[4]
11100LV[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[16][43]MAIN[16][42]MAIN[17][40]MAIN[17][41]MAIN[18][43]HEX_N0[5]
Source
00000off
00001OMUX_NE12
00010HEX_E6[6]
01001OMUX_N12
01010LV[6]
10001HEX_N6[5]
10010HEX_W3[5]
10100HEX_W6[3]
11001HEX_N6[3]
11010HEX_E3[5]
11100LV[18]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[17][51]MAIN[17][50]MAIN[18][50]MAIN[16][48]MAIN[16][49]HEX_N0[6]
Source
00000off
00001OMUX[9]
00010HEX_W6[4]
01001OMUX_WN14
01010HEX_W3[6]
10001HEX_N6[6]
10010HEX_E6[7]
10100LV[0]
11001HEX_N6[4]
11010HEX_E3[6]
11100LV[12]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[16][59]MAIN[16][58]MAIN[17][57]MAIN[18][59]MAIN[17][56]HEX_N0[7]
Source
00000off
00010OMUX_N11
00100HEX_E6_S[0]
01001OMUX[11]
01010OMUX_W9
01100LV[6]
10001HEX_W6[5]
10010HEX_N6[7]
10100HEX_W3[7]
11001LV[18]
11010HEX_N6[5]
11100HEX_E3[7]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LH[0]
BitsDestination
MAIN[18][38]MAIN[18][40]MAIN[18][41]LH[0]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LH[6]
BitsDestination
MAIN[18][25]MAIN[18][22]MAIN[18][23]LH[6]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LH[12]
BitsDestination
MAIN[18][39]MAIN[18][33]MAIN[18][32]LH[12]
Source
000off
001DBL_E1[4]
010DBL_W1[4]
101OMUX[11]
110OMUX_S4
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LH[18]
BitsDestination
MAIN[18][24]MAIN[18][31]MAIN[18][30]LH[18]
Source
000off
001OMUX[4]
010DBL_E1[3]
101OMUX_N15
110DBL_W1[3]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LV[0]
BitsDestination
MAIN[18][8]MAIN[18][7]MAIN[18][1]MAIN[18][6]MAIN[18][0]LV[0]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LV[6]
BitsDestination
MAIN[18][55]MAIN[18][56]MAIN[18][62]MAIN[18][63]MAIN[18][57]LV[6]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LV[12]
BitsDestination
MAIN[18][9]MAIN[18][14]MAIN[18][16]MAIN[18][15]MAIN[18][17]LV[12]
Source
00000off
00001HEX_E5[0]
00010OMUX_E2
00100HEX_E6[0]
01001OMUX[0]
01010DBL_E1[2]
01100HEX_E2[0]
10001HEX_E1[0]
11001HEX_E4[0]
11010HEX_E3[0]
11100DBL_W1[1]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes LV[18]
BitsDestination
MAIN[18][54]MAIN[18][49]MAIN[18][47]MAIN[18][46]MAIN[18][48]LV[18]
Source
00000off
00001DBL_W1[7]
00010OMUX_W9
00100HEX_W1[6]
01001HEX_W3[6]
01010DBL_E1[7]
01100HEX_W0[6]
10010HEX_W2[6]
11001OMUX[15]
11010HEX_W4[6]
11100HEX_W5[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][39]MAIN[5][38]MAIN[4][39]MAIN[4][37]MAIN[4][42]MAIN[4][40]MAIN[5][40]MAIN[4][43]MAIN[4][47]MAIN[5][44]IMUX_CLK[1]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][17]MAIN[5][18]MAIN[4][18]MAIN[4][17]MAIN[5][22]MAIN[4][22]MAIN[4][25]MAIN[5][21]MAIN[5][20]MAIN[4][19]IMUX_CLK[2]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[3]
0001100000DBL_E0[3]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[3]
0010100000DBL_W2[3]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][46]MAIN[5][45]MAIN[4][45]MAIN[4][46]MAIN[5][41]MAIN[4][41]MAIN[4][38]MAIN[5][42]MAIN[5][43]MAIN[4][44]IMUX_CLK[3]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000GCLK[3]
0001010000DBL_E1[4]
0001100000DBL_E0[4]
0010000001GCLK[4]
0010000010GCLK[5]
0010000100GCLK[6]
0010001000GCLK[7]
0010010000DBL_W1[4]
0010100000DBL_W2[4]
0100000001HEX_S3[4]
0100000010HEX_N3[4]
0100000100HEX_S2[4]
0100001000HEX_N4[4]
0100010000HEX_N5[4]
0100100000HEX_S1[4]
1000000001HEX_S6[4]
1000000010HEX_N0[4]
1000000100HEX_S5[4]
1000001000HEX_N1[4]
1000010000HEX_S4[4]
1000100000HEX_N2[4]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[0]
BitsDestination
MAIN[11][27]MAIN[11][29]MAIN[11][28]MAIN[11][26]MAIN[10][31]MAIN[10][26]MAIN[12][25]MAIN[12][31]IMUX_FAN_BX[0]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[1]
BitsDestination
MAIN[8][35]MAIN[8][36]MAIN[8][34]MAIN[9][32]MAIN[8][37]MAIN[9][33]MAIN[8][33]MAIN[10][35]IMUX_FAN_BX[1]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[2]
BitsDestination
MAIN[12][27]MAIN[12][29]MAIN[12][28]MAIN[11][30]MAIN[11][31]MAIN[10][29]MAIN[12][30]MAIN[12][26]IMUX_FAN_BX[2]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BX[3]
BitsDestination
MAIN[9][35]MAIN[9][36]MAIN[9][34]MAIN[10][33]MAIN[8][32]MAIN[9][37]MAIN[8][38]MAIN[10][36]IMUX_FAN_BX[3]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[0]
BitsDestination
MAIN[9][27]MAIN[9][29]MAIN[9][28]MAIN[8][31]MAIN[8][25]MAIN[9][26]MAIN[10][30]MAIN[10][27]IMUX_FAN_BY[0]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[1]
BitsDestination
MAIN[12][35]MAIN[12][34]MAIN[12][36]MAIN[11][33]MAIN[12][37]MAIN[11][32]MAIN[12][33]MAIN[10][34]IMUX_FAN_BY[1]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[2]
BitsDestination
MAIN[8][27]MAIN[8][29]MAIN[8][28]MAIN[8][26]MAIN[8][30]MAIN[9][30]MAIN[9][31]MAIN[10][28]IMUX_FAN_BY[2]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_FAN_BY[3]
BitsDestination
MAIN[11][35]MAIN[11][34]MAIN[11][36]MAIN[11][37]MAIN[12][32]MAIN[10][32]MAIN[12][38]MAIN[10][37]IMUX_FAN_BY[3]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[2]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[9][55]MAIN[9][57]MAIN[8][57]MAIN[9][52]MAIN[8][56]MAIN[10][51]IMUX_DATA[2]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[3]
BitsDestination
MAIN[12][20]MAIN[12][22]MAIN[12][21]MAIN[11][20]MAIN[11][25]MAIN[10][23]MAIN[12][19]MAIN[12][23]IMUX_DATA[3]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[16]
BitsDestination
MAIN[8][42]MAIN[8][43]MAIN[8][41]MAIN[9][38]MAIN[8][40]MAIN[9][43]MAIN[8][44]MAIN[10][41]IMUX_DATA[16]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[17]
BitsDestination
MAIN[11][10]MAIN[11][8]MAIN[11][9]MAIN[11][11]MAIN[11][6]MAIN[10][13]MAIN[12][7]MAIN[12][6]IMUX_DATA[17]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[18]
BitsDestination
MAIN[8][54]MAIN[8][53]MAIN[8][55]MAIN[9][51]MAIN[8][52]MAIN[9][56]MAIN[10][55]MAIN[10][53]IMUX_DATA[18]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[19]
BitsDestination
MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][24]MAIN[10][21]MAIN[10][25]MAIN[12][24]MAIN[12][18]IMUX_DATA[19]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[20]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[9][3]MAIN[8][0]MAIN[8][5]MAIN[9][5]MAIN[10][1]MAIN[10][4]IMUX_DATA[20]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[21]
BitsDestination
MAIN[12][48]MAIN[12][47]MAIN[12][49]MAIN[11][49]MAIN[12][46]MAIN[11][44]MAIN[10][49]MAIN[10][46]IMUX_DATA[21]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[22]
BitsDestination
MAIN[9][17]MAIN[9][16]MAIN[9][15]MAIN[8][12]MAIN[8][13]MAIN[9][18]MAIN[9][13]MAIN[10][18]IMUX_DATA[22]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[23]
BitsDestination
MAIN[12][60]MAIN[12][61]MAIN[12][62]MAIN[11][63]MAIN[12][59]MAIN[10][56]MAIN[10][60]MAIN[11][59]IMUX_DATA[23]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[24]
BitsDestination
MAIN[12][42]MAIN[12][41]MAIN[12][43]MAIN[11][43]MAIN[12][40]MAIN[11][38]MAIN[12][44]MAIN[10][40]IMUX_DATA[24]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[25]
BitsDestination
MAIN[9][10]MAIN[9][8]MAIN[9][9]MAIN[8][6]MAIN[8][7]MAIN[9][11]MAIN[9][6]MAIN[10][12]IMUX_DATA[25]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[26]
BitsDestination
MAIN[12][54]MAIN[12][55]MAIN[12][53]MAIN[11][56]MAIN[12][52]MAIN[11][51]MAIN[10][54]MAIN[10][52]IMUX_DATA[26]
Source
00000000off
00000001OMUX[9]
00000010OMUX_S3
00000100IMUX_FAN_BX[1]
00001000DBL_N2[4]
00100001DBL_S1[4]
00100010OMUX_WS1
00100100DBL_E1[5]
00101000OMUX_N11
00110000IMUX_FAN_BX[0]
01100001OMUX_SE3
01100010OMUX_W9
01100100DBL_S2[4]
01101000DBL_W2[5]
01110000DBL_W1[4]
10000001DBL_S2[5]
10000010DBL_W1[5]
10000100OMUX_E8
10001000DBL_W0[4]
10010000DBL_E2[5]
11000001DBL_N1[4]
11000010DBL_W2[4]
11000100DBL_E1[4]
11001000DBL_E2[4]
11010000DBL_E0[5]
11100001DBL_N1[5]
11100010DBL_N2[5]
11100100DBL_S0[4]
11110000DBL_S1[5]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[27]
BitsDestination
MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[8][18]MAIN[8][24]MAIN[9][24]MAIN[10][20]MAIN[10][24]IMUX_DATA[27]
Source
00000000off
00000001DBL_N1[3]
00000010DBL_N2[3]
00000100DBL_S2[3]
00001000DBL_S0[2]
00010000DBL_S1[2]
00100001OMUX_S4
00100010OMUX_W6
00100100IMUX_FAN_BX[3]
00101000OMUX_N12
00110000DBL_W0[2]
01100001DBL_S2[2]
01100010DBL_E1[3]
01100100DBL_W2[3]
01101000DBL_W1[2]
01110000IMUX_FAN_BX[2]
10000001DBL_N1[2]
10000010DBL_W2[2]
10000100DBL_E2[2]
10001000DBL_E1[2]
10010000DBL_S1[3]
11000001DBL_N2[2]
11000010DBL_W1[3]
11000100OMUX_E7
11001000DBL_E0[3]
11010000DBL_E2[3]
11100001OMUX[6]
11100010OMUX_WN14
11100100OMUX_NE12
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[28]
BitsDestination
MAIN[11][1]MAIN[11][2]MAIN[11][3]MAIN[11][5]MAIN[10][0]MAIN[10][5]MAIN[12][5]MAIN[12][0]IMUX_DATA[28]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[29]
BitsDestination
MAIN[8][48]MAIN[8][49]MAIN[8][47]MAIN[9][44]MAIN[8][46]MAIN[9][49]MAIN[10][48]MAIN[10][47]IMUX_DATA[29]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[30]
BitsDestination
MAIN[11][17]MAIN[11][16]MAIN[11][15]MAIN[11][18]MAIN[11][13]MAIN[10][19]MAIN[12][13]MAIN[12][12]IMUX_DATA[30]
Source
00000000off
00000001DBL_S1[1]
00000010DBL_S0[0]
00000100DBL_N1[1]
00001000DBL_N2[1]
00010000IMUX_FAN_BY[0]
00100001DBL_E1[0]
00100010OMUX_NW10
00101000OMUX_EN8
00110000DBL_W2[1]
01100001OMUX[2]
01100010DBL_E1[1]
01100100DBL_S1[0]
01101000DBL_S2[0]
01110000DBL_S2[1]
10000001DBL_E0[0]
10000010OMUX_W1
10000100DBL_N1[0]
10001000DBL_W2[0]
10010000DBL_E2[0]
11000001DBL_E2[1]
11000010DBL_W1[0]
11000100DBL_N2[0]
11001000DBL_W1[1]
11010000DBL_W0[0]
11100001IMUX_FAN_BY[1]
11100010OMUX_S0
11100100OMUX_E2
11110000OMUX_N10
spartan3 INT_DCM_S3E_DUMMY switchbox INT muxes IMUX_DATA[31]
BitsDestination
MAIN[8][60]MAIN[8][62]MAIN[8][61]MAIN[10][57]MAIN[8][59]MAIN[9][63]MAIN[10][61]MAIN[9][59]IMUX_DATA[31]
Source
00000000off
00000001OMUX[13]
00000010OMUX_SW5
00001000IMUX_FAN_BY[2]
01000001DBL_S2[6]
01000010DBL_E1[7]
01000100DBL_W2[7]
01001000DBL_E0[7]
01010000DBL_S1[6]
01100001OMUX_N15
01100010OMUX_S5
01100100OMUX_ES7
01101000OMUX_E13
01110000OMUX_W14
10000001DBL_N2[6]
10000010DBL_W1[7]
10000100DBL_E2[7]
10001000DBL_W0[6]
10010000DBL_W1[6]
10100001DBL_N1[6]
10100010DBL_W2[6]
10100100DBL_S1[7]
10101000DBL_E2[6]
10110000DBL_E1[6]
11100001DBL_N1[7]
11100010DBL_N2[7]
11100100DBL_S2[7]
11101000IMUX_FAN_BY[3]
11110000DBL_S0[6]

Switchbox PTE2OMUX

spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[12]
BitsDestination
MAIN[3][23]MAIN[3][22]MAIN[3][21]OUT_SEC[12]
Source
000off
001IMUX_DATA[31]
010IMUX_DATA[23]
011IMUX_CLK_OPTINV[3]
100IMUX_DATA[19]
101IMUX_DATA[3]
110IMUX_DATA[27]
spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[13]
BitsDestination
MAIN[3][16]MAIN[3][18]MAIN[3][17]OUT_SEC[13]
Source
000off
001IMUX_DATA[22]
010IMUX_DATA[30]
011IMUX_CLK_OPTINV[2]
100IMUX_DATA[18]
101IMUX_DATA[26]
spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[14]
BitsDestination
MAIN[3][48]MAIN[3][49]MAIN[3][50]OUT_SEC[14]
Source
000off
001IMUX_DATA[29]
010IMUX_DATA[21]
011IMUX_CLK_OPTINV[1]
100IMUX_DATA[17]
101IMUX_DATA[2]
110IMUX_DATA[25]
spartan3 INT_DCM_S3E_DUMMY switchbox PTE2OMUX muxes OUT_SEC[15]
BitsDestination
MAIN[3][42]MAIN[3][41]MAIN[3][40]OUT_SEC[15]
Source
000off
001IMUX_DATA[16]
010IMUX_DATA[20]
011IMUX_DATA[24]
100IMUX_DATA[28]

Bitstream

spartan3 INT_DCM_S3E_DUMMY rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - INT: mux OMUX[15] bit 1 - - INT: mux IMUX_DATA[31] bit 2 - INT: mux IMUX_DATA[23] bit 4 - INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux HEX_E0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux LV[6] bit 1
B62 - - - - - - INT: mux OMUX[15] bit 0 - INT: mux IMUX_DATA[31] bit 6 - - - INT: mux IMUX_DATA[23] bit 5 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux HEX_E0[7] bit 1 INT: mux HEX_W0[7] bit 2 INT: mux LV[6] bit 2
B61 - - - - - - - - INT: mux IMUX_DATA[31] bit 5 - INT: mux IMUX_DATA[31] bit 1 - INT: mux IMUX_DATA[23] bit 6 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 4 INT: mux DBL_E0[7] bit 4 INT: mux HEX_W0[7] bit 3 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0
B60 - - - - - - INT: mux OMUX[14] bit 3 INT: mux OMUX[15] bit 2 INT: mux IMUX_DATA[31] bit 7 - INT: mux IMUX_DATA[23] bit 1 - INT: mux IMUX_DATA[23] bit 7 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 5 INT: mux DBL_E0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 0
B59 - - - - - - INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 2 INT: mux IMUX_DATA[31] bit 3 INT: mux IMUX_DATA[31] bit 0 - INT: mux IMUX_DATA[23] bit 0 INT: mux IMUX_DATA[23] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 5 INT: mux HEX_N0[7] bit 4 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 1
B58 - - - - - - INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 - - - - - INT: mux DBL_S0[7] bit 1 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 4 INT: mux HEX_N0[7] bit 3 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0
B57 - - - - - - INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 5 INT: mux IMUX_DATA[2] bit 3 INT: mux IMUX_DATA[2] bit 4 INT: mux IMUX_DATA[31] bit 4 - - INT: mux DBL_S0[7] bit 0 INT: mux DBL_N0[7] bit 0 INT: mux DBL_S0[7] bit 3 INT: mux HEX_S0[7] bit 1 INT: mux HEX_N0[7] bit 2 INT: mux LV[6] bit 0
B56 - - - - - - INT: mux OMUX[14] bit 0 INT: mux OMUX[14] bit 5 INT: mux IMUX_DATA[2] bit 1 INT: mux IMUX_DATA[18] bit 2 INT: mux IMUX_DATA[23] bit 2 INT: mux IMUX_DATA[26] bit 4 - INT: mux DBL_S0[7] bit 2 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 3 INT: mux HEX_S0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux LV[6] bit 3
B55 - - - - - - INT: mux OMUX[12] bit 1 INT: mux OMUX[12] bit 5 INT: mux IMUX_DATA[18] bit 5 INT: mux IMUX_DATA[2] bit 5 INT: mux IMUX_DATA[18] bit 1 - INT: mux IMUX_DATA[26] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 3 INT: mux HEX_W0[6] bit 2 INT: mux HEX_E0[6] bit 1 INT: mux LV[6] bit 4
B54 - - - - - - INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 5 INT: mux IMUX_DATA[18] bit 7 INT: mux IMUX_DATA[2] bit 7 INT: mux IMUX_DATA[26] bit 1 - INT: mux IMUX_DATA[26] bit 7 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 0 INT: mux DBL_E0[6] bit 3 INT: mux HEX_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux LV[18] bit 4
B53 - - - - - - INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_DATA[18] bit 6 INT: mux IMUX_DATA[2] bit 6 INT: mux IMUX_DATA[18] bit 0 - INT: mux IMUX_DATA[26] bit 5 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 4 INT: mux HEX_E0[6] bit 3 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0
B52 - - - - - - INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 2 INT: mux IMUX_DATA[18] bit 3 INT: mux IMUX_DATA[2] bit 2 INT: mux IMUX_DATA[26] bit 0 - INT: mux IMUX_DATA[26] bit 3 INT: mux DBL_W0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 5 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 0
B51 - - - - - - INT: mux OMUX[12] bit 3 INT: mux OMUX[13] bit 2 - INT: mux IMUX_DATA[18] bit 4 INT: mux IMUX_DATA[2] bit 0 INT: mux IMUX_DATA[26] bit 2 - INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 5 INT: mux DBL_S0[6] bit 5 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 0
B50 - - - PTE2OMUX: mux OUT_SEC[14] bit 0 - - - - - - - - - INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 4 INT: mux DBL_S0[6] bit 4 INT: mux HEX_S0[6] bit 3 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 2
B49 - - - PTE2OMUX: mux OUT_SEC[14] bit 1 - - INT: mux OMUX[13] bit 1 - INT: mux IMUX_DATA[29] bit 6 INT: mux IMUX_DATA[29] bit 2 INT: mux IMUX_DATA[21] bit 1 INT: mux IMUX_DATA[21] bit 4 INT: mux IMUX_DATA[21] bit 5 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux HEX_S0[6] bit 1 INT: mux LV[18] bit 3
B48 - - - PTE2OMUX: mux OUT_SEC[14] bit 2 - - INT: mux OMUX[13] bit 0 - INT: mux IMUX_DATA[29] bit 7 - INT: mux IMUX_DATA[29] bit 1 - INT: mux IMUX_DATA[21] bit 7 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux HEX_N0[6] bit 1 INT: mux HEX_S0[6] bit 2 INT: mux LV[18] bit 0
B47 - - - - INT: mux IMUX_CLK[1] bit 1 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux OMUX[11] bit 1 - INT: mux IMUX_DATA[29] bit 5 - INT: mux IMUX_DATA[29] bit 0 - INT: mux IMUX_DATA[21] bit 6 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_W0[5] bit 2 INT: mux LV[18] bit 2
B46 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[11] bit 0 - INT: mux IMUX_DATA[29] bit 3 - INT: mux IMUX_DATA[21] bit 0 - INT: mux IMUX_DATA[21] bit 3 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux HEX_E0[5] bit 0 INT: mux HEX_W0[5] bit 1 INT: mux LV[18] bit 1
B45 - - - - INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 8 - - - - - - - INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 4 INT: mux DBL_E0[5] bit 4 INT: mux HEX_W0[5] bit 3 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 2
B44 - - - - INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 2 INT: mux IMUX_DATA[16] bit 1 INT: mux IMUX_DATA[29] bit 4 - INT: mux IMUX_DATA[21] bit 2 INT: mux IMUX_DATA[24] bit 1 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 5 INT: mux DBL_E0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 0
B43 - - - - INT: mux IMUX_CLK[1] bit 2 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 2 INT: mux IMUX_DATA[16] bit 6 INT: mux IMUX_DATA[16] bit 2 - INT: mux IMUX_DATA[24] bit 4 INT: mux IMUX_DATA[24] bit 5 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 5 INT: mux DBL_S0[5] bit 5 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 0
B42 - - - PTE2OMUX: mux OUT_SEC[15] bit 2 INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_DATA[16] bit 7 - - - INT: mux IMUX_DATA[24] bit 7 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 4 INT: mux DBL_S0[5] bit 4 INT: mux HEX_N0[5] bit 3 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 2
B41 - - - PTE2OMUX: mux OUT_SEC[15] bit 1 INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 5 INT: mux IMUX_DATA[16] bit 5 - INT: mux IMUX_DATA[16] bit 0 - INT: mux IMUX_DATA[24] bit 6 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 3 INT: mux HEX_S0[5] bit 0 INT: mux HEX_N0[5] bit 1 INT: mux LH[0] bit 0
B40 - - - PTE2OMUX: mux OUT_SEC[15] bit 0 INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 3 INT: mux OMUX[10] bit 0 INT: mux OMUX[10] bit 5 INT: mux IMUX_DATA[16] bit 3 - INT: mux IMUX_DATA[24] bit 0 - INT: mux IMUX_DATA[24] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_N0[5] bit 2 INT: mux LH[0] bit 1
B39 - - - - INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[8] bit 1 INT: mux OMUX[8] bit 5 - - - - - INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux HEX_E0[4] bit 2 INT: mux LH[12] bit 2
B38 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 5 INT: mux IMUX_FAN_BX[3] bit 1 INT: mux IMUX_DATA[16] bit 4 - INT: mux IMUX_DATA[24] bit 2 INT: mux IMUX_FAN_BY[3] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux HEX_W0[4] bit 0 INT: mux HEX_E0[4] bit 1 INT: mux LH[0] bit 2
B37 - - - - INT: mux IMUX_CLK[1] bit 6 INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_FAN_BX[1] bit 3 INT: mux IMUX_FAN_BX[3] bit 2 INT: mux IMUX_FAN_BY[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 4 INT: mux DBL_E0[4] bit 4 INT: mux HEX_E0[4] bit 3 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 2
B36 - - - - - - INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 2 INT: mux IMUX_FAN_BX[1] bit 6 INT: mux IMUX_FAN_BX[3] bit 6 INT: mux IMUX_FAN_BX[3] bit 0 INT: mux IMUX_FAN_BY[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 5 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 5 INT: mux DBL_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 4 INT: mux HEX_E0[4] bit 0
B35 - - - - - - INT: mux OMUX[8] bit 3 INT: mux OMUX[9] bit 2 INT: mux IMUX_FAN_BX[1] bit 7 INT: mux IMUX_FAN_BX[3] bit 7 INT: mux IMUX_FAN_BX[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 7 INT: mux IMUX_FAN_BY[1] bit 7 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 5 INT: mux DBL_S0[4] bit 5 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 0
B34 - - - - - - - - INT: mux IMUX_FAN_BX[1] bit 5 INT: mux IMUX_FAN_BX[3] bit 5 INT: mux IMUX_FAN_BY[1] bit 0 INT: mux IMUX_FAN_BY[3] bit 6 INT: mux IMUX_FAN_BY[1] bit 6 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 4 INT: mux DBL_S0[4] bit 4 INT: mux HEX_S0[4] bit 3 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 2
B33 - - - - - - INT: mux OMUX[9] bit 1 - INT: mux IMUX_FAN_BX[1] bit 1 INT: mux IMUX_FAN_BX[1] bit 2 INT: mux IMUX_FAN_BX[3] bit 4 INT: mux IMUX_FAN_BY[1] bit 4 INT: mux IMUX_FAN_BY[1] bit 1 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux HEX_S0[4] bit 1 INT: mux LH[12] bit 1
B32 - - - - - - INT: mux OMUX[9] bit 0 - INT: mux IMUX_FAN_BX[3] bit 3 INT: mux IMUX_FAN_BX[1] bit 4 INT: mux IMUX_FAN_BY[3] bit 2 INT: mux IMUX_FAN_BY[1] bit 2 INT: mux IMUX_FAN_BY[3] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux HEX_N0[4] bit 1 INT: mux HEX_S0[4] bit 2 INT: mux LH[12] bit 0
B31 - - - - - - INT: mux OMUX[7] bit 1 - INT: mux IMUX_FAN_BY[0] bit 4 INT: mux IMUX_FAN_BY[2] bit 1 INT: mux IMUX_FAN_BX[0] bit 3 INT: mux IMUX_FAN_BX[2] bit 3 INT: mux IMUX_FAN_BX[0] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_W0[3] bit 2 INT: mux LH[18] bit 1
B30 - - - - - - INT: mux OMUX[7] bit 0 - INT: mux IMUX_FAN_BY[2] bit 3 INT: mux IMUX_FAN_BY[2] bit 2 INT: mux IMUX_FAN_BY[0] bit 1 INT: mux IMUX_FAN_BX[2] bit 4 INT: mux IMUX_FAN_BX[2] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux HEX_E0[3] bit 0 INT: mux HEX_W0[3] bit 1 INT: mux LH[18] bit 0
B29 - - - - - - - - INT: mux IMUX_FAN_BY[2] bit 6 INT: mux IMUX_FAN_BY[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 2 INT: mux IMUX_FAN_BX[0] bit 6 INT: mux IMUX_FAN_BX[2] bit 6 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 4 INT: mux DBL_E0[3] bit 4 INT: mux HEX_W0[3] bit 3 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 2
B28 - - - - - - INT: mux OMUX[6] bit 3 INT: mux OMUX[7] bit 2 INT: mux IMUX_FAN_BY[2] bit 5 INT: mux IMUX_FAN_BY[0] bit 5 INT: mux IMUX_FAN_BY[2] bit 0 INT: mux IMUX_FAN_BX[0] bit 5 INT: mux IMUX_FAN_BX[2] bit 5 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 5 INT: mux DBL_E0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 0
B27 - - - - - - INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 2 INT: mux IMUX_FAN_BY[2] bit 7 INT: mux IMUX_FAN_BY[0] bit 7 INT: mux IMUX_FAN_BY[0] bit 0 INT: mux IMUX_FAN_BX[0] bit 7 INT: mux IMUX_FAN_BX[2] bit 7 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 5 INT: mux DBL_S0[3] bit 5 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 4 INT: mux HEX_N0[3] bit 0
B26 - - - - - - INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_FAN_BY[2] bit 4 INT: mux IMUX_FAN_BY[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 2 INT: mux IMUX_FAN_BX[0] bit 4 INT: mux IMUX_FAN_BX[2] bit 0 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 4 INT: mux DBL_S0[3] bit 4 INT: mux HEX_N0[3] bit 3 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 2
B25 - - - - INT: mux IMUX_CLK[2] bit 3 - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 5 INT: mux IMUX_FAN_BY[0] bit 3 - INT: mux IMUX_DATA[19] bit 2 INT: mux IMUX_DATA[3] bit 3 INT: mux IMUX_FAN_BX[0] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_N0[3] bit 1 INT: mux LH[6] bit 2
B24 - - - - - - INT: mux OMUX[6] bit 0 INT: mux OMUX[6] bit 5 INT: mux IMUX_DATA[27] bit 3 INT: mux IMUX_DATA[27] bit 2 INT: mux IMUX_DATA[27] bit 0 INT: mux IMUX_DATA[19] bit 4 INT: mux IMUX_DATA[19] bit 1 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 1 INT: mux DBL_N0[3] bit 3 INT: mux HEX_S0[3] bit 1 INT: mux HEX_N0[3] bit 2 INT: mux LH[18] bit 2
B23 - - - PTE2OMUX: mux OUT_SEC[12] bit 2 - - INT: mux OMUX[4] bit 1 INT: mux OMUX[4] bit 5 - INT: mux IMUX_DATA[27] bit 7 INT: mux IMUX_DATA[3] bit 2 INT: mux IMUX_DATA[19] bit 7 INT: mux IMUX_DATA[3] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 3 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux LH[6] bit 0
B22 - - - PTE2OMUX: mux OUT_SEC[12] bit 1 INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 5 - INT: mux IMUX_DATA[27] bit 6 - INT: mux IMUX_DATA[19] bit 6 INT: mux IMUX_DATA[3] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_W0[2] bit 0 INT: mux DBL_E0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux HEX_E0[2] bit 2 INT: mux LH[6] bit 1
B21 - - - PTE2OMUX: mux OUT_SEC[12] bit 0 - INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 - INT: mux IMUX_DATA[27] bit 5 INT: mux IMUX_DATA[19] bit 3 INT: mux IMUX_DATA[19] bit 5 INT: mux IMUX_DATA[3] bit 5 INT: mux DBL_E0[2] bit 1 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0
B20 - - - - - INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 2 - - INT: mux IMUX_DATA[27] bit 1 INT: mux IMUX_DATA[3] bit 4 INT: mux IMUX_DATA[3] bit 7 INT: mux DBL_W0[2] bit 1 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 5 INT: mux HEX_E0[2] bit 4 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 1
B19 - - - - INT: mux IMUX_CLK[2] bit 0 - INT: mux OMUX[4] bit 3 INT: mux OMUX[5] bit 2 - - INT: mux IMUX_DATA[30] bit 2 - INT: mux IMUX_DATA[3] bit 1 INT: mux DBL_N0[2] bit 1 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 5 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 1
B18 - - - PTE2OMUX: mux OUT_SEC[13] bit 1 INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 8 - - INT: mux IMUX_DATA[27] bit 4 INT: mux IMUX_DATA[22] bit 2 INT: mux IMUX_DATA[22] bit 0 INT: mux IMUX_DATA[30] bit 4 INT: mux IMUX_DATA[19] bit 0 INT: mux DBL_S0[2] bit 1 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0
B17 - - - PTE2OMUX: mux OUT_SEC[13] bit 0 INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[5] bit 1 - - INT: mux IMUX_DATA[22] bit 7 - INT: mux IMUX_DATA[30] bit 7 - INT: mux DBL_S0[2] bit 0 INT: mux DBL_N0[2] bit 0 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux LV[12] bit 0
B16 - - - PTE2OMUX: mux OUT_SEC[13] bit 2 - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux OMUX[5] bit 0 - - INT: mux IMUX_DATA[22] bit 6 - INT: mux IMUX_DATA[30] bit 6 - INT: mux DBL_S0[2] bit 3 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 2 INT: mux HEX_N0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux LV[12] bit 2
B15 - - - - - - INT: mux OMUX[3] bit 1 - - INT: mux IMUX_DATA[22] bit 5 - INT: mux IMUX_DATA[30] bit 5 - INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux LV[12] bit 1
B14 - - - - - - INT: mux OMUX[3] bit 0 - - - - - - INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux HEX_E0[1] bit 0 INT: mux HEX_W0[1] bit 1 INT: mux LV[12] bit 3
B13 - - - - - - - - INT: mux IMUX_DATA[22] bit 3 INT: mux IMUX_DATA[22] bit 1 INT: mux IMUX_DATA[17] bit 2 INT: mux IMUX_DATA[30] bit 3 INT: mux IMUX_DATA[30] bit 1 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 4 INT: mux DBL_E0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 2
B12 - - - - - - INT: mux OMUX[2] bit 3 INT: mux OMUX[3] bit 2 INT: mux IMUX_DATA[22] bit 4 - INT: mux IMUX_DATA[25] bit 0 - INT: mux IMUX_DATA[30] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 5 INT: mux DBL_E0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 0
B11 - - - - - - INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 2 - INT: mux IMUX_DATA[25] bit 2 - INT: mux IMUX_DATA[17] bit 4 - INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 5 INT: mux DBL_S0[1] bit 5 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 0
B10 - - - - - - INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 - INT: mux IMUX_DATA[25] bit 7 - INT: mux IMUX_DATA[17] bit 7 - INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 4 INT: mux DBL_S0[1] bit 4 INT: mux HEX_N0[1] bit 3 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 2
B9 - - - - - - INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 5 - INT: mux IMUX_DATA[25] bit 5 - INT: mux IMUX_DATA[17] bit 5 - INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux HEX_S0[1] bit 0 INT: mux HEX_N0[1] bit 1 INT: mux LV[12] bit 4
B8 - - - - - - INT: mux OMUX[2] bit 0 INT: mux OMUX[2] bit 5 - INT: mux IMUX_DATA[25] bit 6 - INT: mux IMUX_DATA[17] bit 6 - INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_N0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_N0[1] bit 2 INT: mux LV[0] bit 4
B7 - - - - - - INT: mux OMUX[0] bit 1 INT: mux OMUX[0] bit 5 INT: mux IMUX_DATA[25] bit 3 - - - INT: mux IMUX_DATA[17] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux HEX_W0[0] bit 1 INT: mux HEX_E0[0] bit 2 INT: mux LV[0] bit 3
B6 - - - - - - INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 5 INT: mux IMUX_DATA[25] bit 4 INT: mux IMUX_DATA[25] bit 1 - INT: mux IMUX_DATA[17] bit 3 INT: mux IMUX_DATA[17] bit 0 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_E0[0] bit 1 INT: mux LV[0] bit 1
B5 - - - - - - INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_DATA[20] bit 3 INT: mux IMUX_DATA[20] bit 2 INT: mux IMUX_DATA[28] bit 2 INT: mux IMUX_DATA[28] bit 4 INT: mux IMUX_DATA[28] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 4 INT: mux DBL_E0[0] bit 4 INT: mux HEX_E0[0] bit 3 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 2
B4 - - - - - - INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 2 - - INT: mux IMUX_DATA[20] bit 0 - - INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 5 INT: mux DBL_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 4 INT: mux HEX_E0[0] bit 0
B3 - - - - - - INT: mux OMUX[0] bit 3 INT: mux OMUX[1] bit 2 - INT: mux IMUX_DATA[20] bit 5 - INT: mux IMUX_DATA[28] bit 5 - INT: mux DBL_N0[0] bit 1 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 5 INT: mux HEX_S0[0] bit 4 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 1
B2 - - - - - - - - - INT: mux IMUX_DATA[20] bit 6 - INT: mux IMUX_DATA[28] bit 6 - INT: mux DBL_S0[0] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 4 INT: mux HEX_S0[0] bit 3 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0
B1 - - - - - - INT: mux OMUX[1] bit 1 - - INT: mux IMUX_DATA[20] bit 7 INT: mux IMUX_DATA[20] bit 1 INT: mux IMUX_DATA[28] bit 7 - INT: mux DBL_S0[0] bit 0 INT: mux DBL_N0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux HEX_S0[0] bit 2 INT: mux LV[0] bit 2
B0 - - - - - - INT: mux OMUX[1] bit 0 - INT: mux IMUX_DATA[20] bit 4 - INT: mux IMUX_DATA[28] bit 3 - INT: mux IMUX_DATA[28] bit 0 INT: mux DBL_S0[0] bit 3 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 2 INT: mux HEX_N0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux LV[0] bit 0